SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D -- APRIL 1991 -- REVISED SEPTEMBER 2004
D
Class B High-Reliability Processing
D
1-μm CMOS Technology
D
Military Operating Temperature Range
D
D
D
Flexible Multi-Processor Interface
D
Packaging Options
D
D
D
D
D
D
D
D
-
-55°C to 125°C
SMJ34020A-32/40
125/100-ns Instruction Cycle Time
Fully Programmable 32-Bit
General-Purpose Processor With
512-Megabyte Linear Address Range
(Bit Addressable)
Second-Generation Graphics System
Processor
- Object-Code Compatible With the
-
SMJ34010
- Enhanced Instruction Set
-
- Optimized Graphics Instructions
-
- Coprocessor Interface
-
Pixel Processing, XY Addressing, and
Window Checking Built Into the Instruction
Set
Programmable 1-, 2-, 4-, 8-, 16-, or 32-Bit
Pixel Size With 16 Boolean and Six
Arithmetic Pixel Processing Options
(Raster Ops)
512-Byte LRU On-Chip Instruction Cache
Optimized DRAM/VRAM Interface
- Page-Mode for Burst Memory Operations
-
- Dynamic Bus Sizing (16-Bit and
-
32-Bit Transfers)
- Byte-Oriented CAS Strobes
-
Flexible Host Processor Interface
- Supports Host Transfers
-
- Direct Access to All of the SMJ34020A
-
Address Space
- Implicit Addressing
-
- Prefetch for Enhanced Read Access
-
Programmable CRT Control
- Composite Sync Mode
-
- Separate Sync Mode
-
- Synchronization to External Sync
-
Direct Support for Special Features of
1M VRAMs
- Load Write Mask
-
- Load Color Mask
-
- Block Write
-
- Write Using the Write Mask
-
- 145-Pin Grid Array Ceramic Package
-
(GB Suffix)
- 132-Pin Ceramic Quad Flat Pack
-
(Unformed Lead) (HT Suffix)
145-PIN GRID ARRAY PACKAGE
(TOP VIEW)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
132-PIN QUAD FLATPACK
(TOP VIEW)
132
100
1
99
33
67
34
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
2004, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
66
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•
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1
SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D -- APRIL 1991 -- REVISED SEPTEMBER 2004
description
The SMJ34020A graphics system processor (GSP) is the second generation of an advanced high-performance
CMOS 32-bit microprocessor optimized for graphics display systems. With a built-in instruction cache, the ability
to simultaneously access memory and registers, and an instruction set designed to expedite raster graphics
operations, the SMJ34020A provides user-programmable control of the CRT interface as well as the memory
interface (both standard DRAM and multiport video RAM). The 4-gigabit (512-megabyte) physical address
space is addressable on bit boundaries using variable width data fields (1 to 32 bits). Additional graphics
addressing modes support 1-, 2-, 4-, 8-, 16- and 32-bit wide pixels.
architecture
The SMJ34020A is a CMOS 32-bit processor with hardware support for graphics operations such as pixel block
transfers (PIXBLTS) during raster operations and curve-drawing algorithms. Also included is a complete set of
general-purpose instructions with addressing modes tuned to support high-level languages. In addition to its
ability to address a large external memory range, the SMJ34020A contains 30 general-purpose 32-bit registers,
a hardware stack pointer, and a 512-byte instruction cache. On-chip functions include 64 programmable I/O
registers that control CRT timing, input/output control, and parameters required by some instructions. The
SMJ34020A directly interfaces to DRAMs and VRAMs and generates raster control signals. The SMJ34020A
can be configured to operate as a standalone processor, or it can be used as a graphics engine with a host
system. The host interface provides a generalized communication port for any standard host processor. The
SMJ34020A also accommodates a multiprocessing or direct memory access (DMA) environment through the
request/grant interface protocols. Virtual memory systems are supported through bus-fault detection and
instruction continuation.
The SMJ34020A provides single-cycle execution of general-purpose instructions and most common integer
arithmetic and Boolean operations from its instruction cache. Additionally, the SMJ34020A incorporates a
hardware barrel shifter that provides a single-state bidirectional shift-and-rotate function for 1 to 32 bits.
The local-memory controller is designed to optimize memory access operations. It also supports pipeline
memory write operations of variable-sized fields and allows memory access and instruction execution in
parallel.
The SMJ34020A graphics-processing hardware supports pixel and pixel-array processing capabilities for both
monochrome and color systems at a variety of pixel sizes. The hardware incorporates two-operand and
three-operand raster operations with Boolean and arithmetic operations, XY addressing, window clipping,
window-checking operations, 1 to
n
bits-per-pixel transforms, transparency, and plane masking. The
architecture further supports operations on single pixel transfer (PIXT) instructions or on two-dimensional
arrays of arbitrary size (PIXBLTS).
The SMJ34020A’s flexible graphics-processing capabilities allow software-based graphics algorithms without
sacrificing performance. These algorithms include clipping to arbitrary window size, custom incremental-curve
drawing, two-operand raster operations, and masked two-operand raster operations.
The SMJ34020A provides for extensions to the basic architecture through the coprocessor interface. Special
instructions and cycle timings are included to enhance data flow to coprocessors without requiring the
coprocessor to decode the instruction stream, generate system addresses, or move data for the coprocessor
through the SMJ34020A.
2
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•
HOUSTON, TEXAS 77251--1443
SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D -- APRIL 1991 -- REVISED SEPTEMBER 2004
Pin Assignments - 145-Pin Grid Array Package
-
PIN
NUMBER
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
C1
C2
C3
C4
C5
C6
C7
C8
†
PIN
NAME
V
SS
ALTCH
NUMBER
C9
C10
C11
C12
C13
C14
C15
D1
D2
D3
D4
†
D13
D14
D15
E1
E2
E3
E13
E14
E15
F1
F2
F3
F13
F14
F15
G1
G2
G3
G13
G14
G15
H1
H2
H3
H13
H14
H15
NAME
RCA8
RCA12
LAD30
V
SS
V
SS
V
CC
LAD26
RAS
CAS2
V
SS
NU
†
LAD28
LAD11
LAD10
R1
V
CC
CAS1
LAD27
LAD25
LAD9
HRDY
R0
V
SS
LAD24
LAD8
V
SS
HINT
HOE
HDST
LAD7
V
SS
LAD23
LCLK1
EMU3
LCLK2
LAD22
LAD21
LAD6
NUMBER
J1
J2
J3
J13
J14
J15
K1
K2
K3
K13
K14
K15
L1
L2
L3
L13
L14
L15
M1
M2
M3
M13
M14
M15
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N13
N14
PIN
NAME
EMU0
GI
EMU1
LAD4
V
CC
LAD5
EMU2
RESET
LINT2
V
SS
LAD3
LAD20
LINT1
CAMD
LRDY
LAD1
LAD2
LAD19
BUSFLT
PGMD
VCLK
V
SS
LAD16
LAD18
SIZE16
V
CC
CLKIN
V
SS
HA29
HA25
HA21
V
SS
V
SS
HA12
HA6
HBS2
HBS1
V
CC
NUMBER
N15
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
PIN
NAME
LAD17
V
CC
HWRITE
HCS
HA30
HA27
HA24
HA22
HA18
HA14
HA13
HA10
HA7
HA5
HBS0
LAD0
HREAD
HA31
HA28
HA26
HA23
HA20
HA19
HA17
HA16
HA15
HA11
HA9
HA8
HBS3
V
SS
CBLNK/VBLNK
HSYNC
TR/QE
RCA2
RCA3
V
CC
RCA6
RCA7
RCA10
SCLK
LAD15
LAD29
V
SS
CAS3
WE
V
SS
CSYNC/HBLNK
VSYNC
RCA0
RCA1
RCA5
RCA9
RCA11
LAD31
LAD14
V
CC
LAD13
LAD12
CAS0
V
CC
DDOUT
DDIN
V
SS
SF
RCA4
V
SS
This pin is provided for device orientation purpose only. Make no external connection.
POST OFFICE BOX 1443
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HOUSTON, TEXAS 77251--1443
3
SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D -- APRIL 1991 -- REVISED SEPTEMBER 2004
Pin Assignments - 132-Pin Ceramic Quad Flatpack Package
-
PIN
NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
NAME
CAS3
CAS2
CAS1
CAS0
V
CC
RAS
V
SS
R0
R1
HOE
HDST
HRDY
HINT
EMU3
LCLK1
LCLK2
EMU1
EMU0
EMU2
GI
RESET
LINT2
LINT1
CAMD
BUSFLT
SIZE16
PGMD
LRDY
V
CC
VCLK
CLKIN
HWRITE
HREAD
NUMBER
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
PIN
NAME
HCS
HA31
HA30
HA29
HA28
HA27
HA26
HA25
HA24
HA23
HA22
HA21
HA20
HA19
HA18
HA17
V
SS
HA16
HA15
HA14
HA13
HA12
HA11
HA10
HA9
HA8
HA7
HA6
HA5
HBS3
HBS2
HBS1
HBS0
NUMBER
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
PIN
NAME
LAD0
LAD16
LAD1
LAD17
LAD2
LAD18
V
SS
LAD3
LAD19
V
CC
LAD4
LAD20
LAD5
LAD21
LAD6
LAD22
LAD7
LAD23
V
SS
V
SS
LAD8
LAD24
LAD9
LAD25
LAD10
LAD26
LAD11
LAD27
V
CC
LAD12
LAD28
V
SS
LAD13
NUMBER
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
PIN
NAME
LAD29
LAD14
LAD30
LAD15
LAD31
SCLK
RCA12
RCA11
RCA10
RCA9
RCA8
RCA7
RCA6
RCA5
V
CC
V
SS
RCA4
RCA3
RCA2
RCA1
RCA0
SF
TR/QE
VSYNC
HSYNC
CBLNK/VBLNK
CSYNC/HBLNK
V
SS
V
SS
ALTCH
DDIN
DDOUT
WE
4
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HOUSTON, TEXAS 77251--1443
SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D -- APRIL 1991 -- REVISED SEPTEMBER 2004
Terminal Functions
TERMINAL
NAME
TYPE
†
DESCRIPTION
LOCAL MEMORY INTERFACE
ALTCH
O
Address latch. The high-to-low transitions of ALTCH can be used to capture the address and status available on LAD.
A transparent latch (such as a 54ALS373) maintains the current address and status as long as ALTCH remains low.
Bus fault. External logic asserts BUSFLT high to the SMJ34020A to indicate that an error or fault has occurred on the
current bus cycle. BUSFLT is also used with LRDY to generate externally requested bus cycle retries so that the entire
memory address is presented again on LAD.
In the emulation mode, BUSFLT is used for write protecting mapped memory (by disabling CAS outputs for the current
cycle).
DDIN
DDOUT
LAD0--LAD31
O
O
I/O
Data bus direction in enable. DDIN is used to drive the active-high output enables on bidirectional transceivers (such
as the 54ALS623). The transceivers buffer data input and output on LAD0--LAD31 when the SMJ34020A is interfaced
to several memories.
Data bus direction output enable. DDOUT drives the active-low output enables on bidirectional transceivers (such as
the 54ALS623). The transceivers buffer data input and output on LAD0--LAD31.
32-bit multiplexed local address/data bus. At the beginning of a memory cycle, the word address is output on
LAD4--LAD31 and the cycle status is output on LAD0--LAD3. After the address is presented, LAD0--LAD31 are used
for transferring data within the SMJ34020A system. LAD0 is the LSB and LAD31 is the MSB.
Local ready. External circuitry drives LRDY low to inhibit the SMJ34020A from completing a local-memory cycle it has
initiated. While LRDY remains low, the SMJ34020A waits unless the SMJ34020A loses bus priority or is given an
external RETRY request (through BUSFLT). Wait states are generated in increments of one full LCLK1 cycle. LRDY can
be driven low to extend local memory-read and memory-write cycles, VRAM serial-data-register-transfer cycles, and
DRAM-refresh cycles. During internal cycles, the SMJ34020A ignores LRDY.
Page mode. The memory-decode logic asserts PGMD low if the currently addressed memory supports burst (page
mode) accesses. Burst accesses occur as a series of CAS cycles for a single RAS cycle to memory. LRDY is used with
BUSFLT to describe the cycle termination status for a memory cycle.
PGMD is also used in emulation mode for mapping memory.
SIZE16
I
Bus size. The memory-decode logic can pull SIZE16 low if the currently addressed memory or port supports only 16-bit
transfers. SIZE16 can also be used to determine which 16 bits of the data bus are used for a data transfer.
In the emulation mode, SIZE16 is used to select the size of mapped memory.
DRAM AND VRAM CONTROL
CAMD
CAS0--CAS3
RAS
I
O
O
Column-address mode. CAMD dynamically shifts the column address on the RCA0--RCA12 bus to allow the mixing
of DRAM and VRAM address matrices using the same multiplexed address RCA0--RCA12 signals.
Four column-address strobes. CAS outputs drive the CAS inputs of DRAMs and VRAMs. CAS0--CAS3 strobe the
column address on RCA0--RCA12 to the memory. The four CAS strobes provide byte write-access to the memory.
Row-address strobe. RAS output drives the RAS inputs of DRAMs and VRAMs. RAS strobes the row address on
RCA0--RCA12 to memory.
Thirteen multiplexed row-address/column-address signals. At the beginning of a memory-access cycle, the row address
for DRAMs is present on RCA0--RCA12. The row address contains the most significant address bits for the memory.
As the cycle progresses, the memory column address is placed on RCA0--RCA12. The addresses that are actually
output during row and column times depend on the memory configuration (set by RCM0 and RCM1 in the CONFIG
register) and the state of CAMD during the access. RCA0 is the LSB, and RCA12 is the MSB.
Special function pin. SF is the special-function signal to 1M VRAMs that allows the use of block write, load write mask,
load color mask, and write using write mask. SF is also used to differentiate instructions and addresses for the
coprocessor as part of the coprocessor interface.
Transfer/output-enable. TR/QE drives the TR/QE input of VRAMs. During a local memory-read cycle, TR/QE functions
as an active-low output enable to gate from memory to LAD0--LAD31. During special VRAM function cycles, TR/QE
controls the type of cycle that is performed.
BUSFLT
I
LRDY
I
PGMD
I
RCA0--RCA12
O
SF
O
TR/QE
†
O
I = input, O = output
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5
stm32/stm8
