Fully synchronous operation for counting and programming
Internal look-ahead for fast counting
Carry output for n-bit cascading
Fully independent clock circuit
1.2μ
CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 16-pin DIP
- 16-lead flatpack
UT54ACS169 - SMD 5962-96560
UT54ACTS169 - SMD 5962-96561
DESCRIPTION
The UT54ACS169 and the UT54ACTS169 are synchronous 4-
bit binary counters that feature an internal carry look-ahead for
cascading in high-speed counting applications. Synchronous
operation is provided by having all flip-flops clocked simulta-
neously so that the outputs change coincident with each other
when instructed by the count-enable inputs and internal gating.
Synchronous operation helps eliminate the output counting
spikes that are normally associated with asynchronous (ripple
clock) counters. The clock input triggers the four flip-flops on
the rising (positive-going) edge of the clock.
The counters are fully programmable (i.e., the outputs may each
be preset high or low). The load input circuitry allows loading
with the carry-enable output of cascaded counters. Loading is
synchronous; applying a low level at the load input disables the
counter and causes the outputs to agree with the data inputs after
the next clock pulse.
The carry look-ahead circuitry provides for cascaded counters
for n-bit synchronous application without additional gating. In-
strumental in accomplishing this function are two count-enable
inputs and a carry output. Assert both count enable inputs (ENP
and ENT) to count. The direction of the count is determined by
the level of the U/D input. When U/D is high, the counter counts
up; when low, it counts down. Input ENT is fed forward to
enable the carry output. The ripple carry output
RCO enables a low-level pulse while the count is zero (all inputs
low) counting down or maximum (15) counting up. The low-
level overflow carry pulse can be used to enable successive cas-
caded stages.
PINOUTS
16-Pin DIP
Top View
U/D
CLK
A
B
C
D
ENP
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
RCO
Q
A
Q
B
Q
C
Q
D
ENT
LOAD
16-Lead Flatpack
Top View
U/D
CLK
A
B
C
D
ENP
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
RCO
Q
A
Q
B
Q
C
Q
D
ENT
LOAD
Transitions at ENP or ENT are allowed regardless of the level
of the clock input.
The counters feature a fully independent clock circuit. Changes
at control inputs (ENP, ENT, LOAD, U/D) that modify the op-
erating mode have no effect on the contents of the counter until
clocking occurs. The function of the counter (whether enabled,
disabled, loading, or counting) will be dictated solely by the
conditions meeting the stable setup and hold times.
The devices are characterized over full military temperature
range of -55°C to +125°C.
1
LOGIC SYMBOL
LOAD
U/D
ENT
(9)
(1)
(10)
CTRDIV 16
M1 (LOAD)
M2 (COUNT)
M3 (UP)
M4 (DOWN)
3,5CT = 15
G5
4,5CT = 0
G6
2,3,5,6+/C7
2,3,5,6-
1,7D
(1)
(2)
(4)
(8)
(14)
(13)
(12)
(11)
Q
A
Q
B
Q
C
Q
D
(15)
FUNCTION TABLE
OUTPUT
Count Up
Count Down
RCO
Load Preset
Inhibit
LOAD
H
H
L
H
H
ENP
L
L
X
H
X
ENT
L
L
X
X
H
U/D
H
L
X
X
X
CLK
↑
↑
↑
X
X
(7)
ENP
(2)
CLK
(4)
B
(5)
C
(6)
D
A
(3)
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC
Publication 617-12.
2
LOGIC DIAGRAM
CLK
U/D
(2)
(1)
DQ
C
LOAD (9)
ENP
ENT
(7)
(10)
DQ
C
Q
A
(3)
(13) Q
1
Q
(14)
Q
0
(4)
B
DQ
C
Q
(12)
Q
2
C
(5)
DQ
C
Q
(11)
D
(6)
Q
3
(15) RCO
3
OPERATIONAL ENVIRONMENT
1
PARAMETER
Total Dose
SEU Threshold
2
SEL Threshold
Neutron Fluence
LIMIT
1.0E6
80
120
1.0E14
UNITS
rads(Si)
MeV-cm
2
/mg
MeV-cm
2
/mg
n/cm
2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
DD
V
I/O
T
STG
T
J
T
LS
Θ
JC
I
I
P
D
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
PARAMETER
Supply voltage
Voltage any pin
Storage Temperature range
Maximum junction temperature
Lead temperature (soldering 5 seconds)
Thermal resistance junction to case
DC input current
Maximum power dissipation
LIMIT
-0.3 to 7.0
-.3 to V
DD
+.3
-65 to +150
+175
+300
20
±10
1
UNITS
V
V
°C
°C
°C
°C/W
mA
W
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
V
IN
T
C
PARAMETER
Supply voltage
Input voltage any pin
Temperature range
LIMIT
4.5 to 5.5
0 to V
DD
-55 to + 125
UNITS
V
V
°C
4
DC ELECTRICAL CHARACTERISTICS
7
(V
DD
= 5.0V
±
10%; V
SS
= 0V
6
, -55°C < T
C
< +125°C); Unless otherwise noted, Tc is per the temperature range ordered.
FPGA/CPLD
