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5962H9654201QCX

NAND Gate, AC Series, 4-Func, 2-Input, CMOS, CDIP14, SIDE BRAZED, CERAMIC, DIP-14

器件类别:逻辑    逻辑   

厂商名称:Cobham Semiconductor Solutions

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器件参数
参数名称
属性值
零件包装代码
DIP
包装说明
DIP,
针数
14
Reach Compliance Code
unknown
ECCN代码
3A001.A.1.A
系列
AC
JESD-30 代码
R-CDIP-T14
长度
19.43 mm
逻辑集成电路类型
NAND GATE
功能数量
4
输入次数
2
端子数量
14
最高工作温度
125 °C
最低工作温度
-55 °C
封装主体材料
CERAMIC, METAL-SEALED COFIRED
封装代码
DIP
封装形状
RECTANGULAR
封装形式
IN-LINE
传播延迟(tpd)
15 ns
认证状态
Not Qualified
座面最大高度
5.08 mm
最大供电电压 (Vsup)
5.5 V
最小供电电压 (Vsup)
4.5 V
标称供电电压 (Vsup)
5 V
表面贴装
NO
技术
CMOS
温度等级
MILITARY
端子形式
THROUGH-HOLE
端子节距
2.54 mm
端子位置
DUAL
总剂量
1M Rad(Si) V
宽度
7.62 mm
Base Number Matches
1
文档预览
Standard Products
UT54ACS132/UT54ACTS132
Quadruple 2-Input NAND Schmitt Triggers
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
1.2μ
CMOS (ACTS 132) and 0.6μ CRH CMOS process
(ACS132)
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 14-pin DIP (not available for the ACS132)
- 14-lead flatpack
UT54ACS132 - SMD 5962-96542
UT54ACTS132 - SMD 5962-96543
DESCRIPTION
The UT54ACS132 and the UT54ACTS132 are 2-input NAND
gates with Schmitt Trigger input levels. A high applied on both
the inputs forces the output to a low state.
The devices are characterized over full military temperature
range of -55°C to +125°C.
FUNCTION TABLE
INPUTS
An
L
L
H
H
Bn
L
H
L
H
OUTPUT
Yn
H
H
H
L
PINOUTS
14-Pin DIP
Top View
A1
B1
Y1
A2
B2
Y2
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
B4
A4
Y4
B3
A3
Y3
14-Lead Flatpack
Top View
A1
B1
Y1
A2
B2
Y2
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
B4
A4
Y4
B3
A3
Y3
LOGIC DIAGRAM
A1
B1
A2
B2
Y1
Y2
LOGIC SYMBOL
A1
B1
A2
B2
A3
B3
A4
B4
(1)
(2)
(4)
(5)
(9)
(10)
(12)
(13)
(11)
(6)
(8)
Y2
Y3
Y4
&
(3)
Y1
A3
B3
A4
B4
Y4
Y3
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984
and IEC Publication 617-12.
1
OPERATIONAL ENVIRONMENT
1
PARAMETER
Total Dose
SEU Threshold
2
SEL Threshold
Neutron Fluence
LIMIT
1.0E6 (ACTS132)
5.0E5 (ACS132)
80
120
1.0E14
UNITS
rads(Si)
MeV-cm
2
/mg
MeV-cm
2
/mg
n/cm
2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
DD
V
I/O
T
STG
T
J
T
LS
Θ
JC
I
I
P
D
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
PARAMETER
Supply voltage
Voltage any pin
Storage Temperature range
Maximum junction temperature
Lead temperature (soldering 5 seconds)
Thermal resistance junction to case
DC input current
Maximum power dissipation
LIMIT
-0.3 to 7.0
-.3 to V
DD
+.3
-65 to +150
+175
+300
20
±10
1
UNITS
V
V
°C
°C
°C
°C/W
mA
W
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
V
IN
T
C
PARAMETER
Supply voltage
Input voltage any pin
Temperature range
LIMIT
4.5 to 5.5
0 to V
DD
-55 to + 125
UNITS
V
V
°C
2
DC ELECTRICAL CHARACTERISTICS
7
(V
DD
= 5.0V
±
10%; V
SS
= 0V
6
, -55°C < T
C
< +125°C); Unless otherwise noted, Tc is per the temperature range ordered.
SYMBOL
V
T
+
PARAMETER
Schmitt Trigger, positive going
1
threshold
ACTS
ACS
Schmitt Trigger, negative going
1
threshold
ACTS
ACS
Schmitt Trigger, typical range of hysteresis
2
CONDITION
MIN
MAX
2.25
.7V
DD
UNIT
V
V
T
-
0.5
.3V
DD
0.3
0.6
0.9
1.5
V
V
H
V
ACTS
ACS
I
IN
V
OL
Input leakage current
ACTS/ACS
Low-level output voltage
3
ACTS
ACS
High-level output voltage
3
ACTS
ACS
Short-circuit output current
2 ,4
ACTS/ACS
Output current
10
(Sink)
I
OH
Output current
10
(Source)
P
total
I
DDQ
ΔI
DDQ
Power dissipation
2, 8, 9
Quiescent Supply Current
Quiescent Supply Current Delta
ACTS
V
IN
= V
DD
or V
SS
I
OL
= 8.0mA
I
OL
= 100μA
I
OH
= -8.0mA
I
OH
= -100μA
V
O
= V
DD
and V
SS
V
IN
= V
DD
or V
SS
V
OL
= 0.4V
V
IN
= V
DD
or V
SS
V
OH
= V
DD
- 0.4V
C
L
= 50pF
V
DD
= 5.5V
For input under test
V
IN
= V
DD
- 2.1V
For all other inputs
V
IN
= V
DD
or V
SS
V
DD
= 5.5V
C
IN
C
OUT
Input capacitance
5
Output capacitance
5
ƒ
= 1MHz @ 0V
ƒ
= 1MHz @ 0V
-1
1
0.40
0.25
μA
V
V
OH
.7V
DD
V
DD
- 0.25
-200
8
200
V
I
OS
I
OL
mA
mA
-8
mA
1.9
10
3.1
mW/
MHz
μA
mA
15
15
pF
pF
3
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V
IH
= V
IH
(min) + 20%, - 0%; V
IL
= V
IL
(max) + 0%, -
50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to V
IH
(min) and V
IL
(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density
5.0E5 amps/cm
2
, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and V
SS
at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All ACTS specifications are valid for radiation dose <1E6 rads(Si), and all ACS specifications are valid for radiation dose <5E5 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
4
AC ELECTRICAL CHARACTERISTICS
2
(V
DD
= 5.0V
±10%;
V
SS
= 0V
1
, -55°C < T
C
< +125°C); Unless otherwise noted, Tc is per the temperature range ordered.
SYMBOL
t
PHL
t
PLH
Input to Yn
Input to Yn
PARAMETER
MINIMUM
2
2
MAXIMUM
15
12
UNIT
ns
ns
Notes:
1. Maximum allowable relative shift equals 50mV.
2. For the ACTS version, all specifications are valid for radiation dose <1E6 rads(Si). For the ACS version, all specifications are valid for radiation dose <5E5 rads(Si).
5
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