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5962H9654401QEA

Decoder/Driver, AC Series, Inverted Output, CMOS, CDIP16, CERAMIC, DIP-16

器件类别:逻辑    逻辑   

厂商名称:Cobham PLC

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器件参数
参数名称
属性值
包装说明
DIP, DIP16,.3
Reach Compliance Code
unknown
ECCN代码
3A001.A.1.A
系列
AC
输入调节
STANDARD
JESD-30 代码
R-GDIP-T16
JESD-609代码
e0
负载电容(CL)
50 pF
逻辑集成电路类型
OTHER DECODER/DRIVER
最大I(ol)
0.008 A
功能数量
1
端子数量
16
最高工作温度
125 °C
最低工作温度
-55 °C
输出极性
INVERTED
封装主体材料
CERAMIC, GLASS-SEALED
封装代码
DIP
封装等效代码
DIP16,.3
封装形状
RECTANGULAR
封装形式
IN-LINE
电源
5 V
Prop。Delay @ Nom-Sup
17 ns
传播延迟(tpd)
15 ns
认证状态
Qualified
筛选级别
MIL-PRF-38535 Class Q
最大供电电压 (Vsup)
5.5 V
最小供电电压 (Vsup)
4.5 V
标称供电电压 (Vsup)
5 V
表面贴装
NO
技术
CMOS
温度等级
MILITARY
端子面层
TIN LEAD
端子形式
THROUGH-HOLE
端子节距
2.54 mm
端子位置
DUAL
总剂量
1M Rad(Si) V
Base Number Matches
1
文档预览
REVISIONS
LTR
A
B
C
D
E
F
DESCRIPTION
Changes in accordance with NOR 5962-R122-97.
Incorporate revision A. Update boilerplate to MIL-PRF-38535
requirements. – LTG
Add appendix A. Editorial changes throughout. – LTG
Correct title. Add device types 02 and 03. Update radiation hardness
assurance paragraphs. Add table IB. - jak
Add equivalent test circuit and footnote 5 in figure 4. - MAA
To correct switching waveforms input/output test limits to figure 4. Add test
equivalent circuits and footnote 4 to figure 4. Delete class M requirements
throughout.-- MAA
DATE (YR-MO-DA)
96-12-10
01-10-02
04-10-19
10-11-19
12-05-10
12-12-10
APPROVED
Monica L. Poelking
Thomas M. Hess
Thomas M. Hess
Muhammad A. Akbar
Thomas M. Hess
Thomas M. Hess
REV
SHEET
REV
SHEET
REV STATUS
OF SHEETS
PMIC N/A
F
15
F
16
F
17
F
18
REV
SHEET
PREPARED BY
Thanh V. Nguyen
F
19
F
20
F
21
F
1
F
22
F
2
F
23
F
3
F
4
F
5
F
6
F
7
F
8
F
9
F
10
F
11
F
12
F
13
F
14
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
CHECKED BY
Thanh V. Nguyen
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil
APPROVED BY
Monica L. Poelking
DRAWING APPROVAL DATE
96-04-12
MICROCIRCUIT, DIGITAL, ADVANCED CMOS,
RADIATION HARDENED, 3-LINE TO 8-LINE
DECODER/DEMULTIPLEXER, MONOLITHIC
SILICON
SIZE
CAGE CODE
REVISION LEVEL
F
AMSC N/A
DSCC FORM 2233
APR 97
A
67268
5962-96544
SHEET 1 OF 23
5962-E082-13
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device class Q) and
space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or
Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.
1.2 PIN. The PIN is as shown in the following example:
5962
Federal
stock class
designator
\
H
RHA
designator
(see 1.2.1)
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are
marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
01
Generic number
54ACS138
Circuit function
Radiation hardened, 3-line to 8-line
decoder/demultiplexer
Enhanced, radiation hardened,
3-line to 8-line decoder/demultiplexer
Enhanced, radiation hardened,
3-line to 8-line decoder/demultiplexer
96544
01
Device
type
(see 1.2.2)
V
Device
class
designator
(see 1.2.3)
X
Case
outline
(see 1.2.4)
C
Lead
finish
(see 1.2.5)
/
02
54ACS138E
03
54ACS138E
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as
follows:
Device class
Q or V
Device requirements documentation
Certification and qualification to MIL-PRF-38535
1.2.4 Case outlines. The case outlines are as designated in MIL-STD-1835 and as follows:
Outline letter
E
X
Descriptive designator
GDIP1-T16 or CDIP2-T16
CDFP4-F16
Terminals
16
16
Package style
Dual-in-line
Flat pack
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V.
.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
A
REVISION LEVEL
5962-96544
SHEET
F
2
1.3 Absolute maximum ratings. 1/ 2/ 3/
Supply voltage range (V
DD
) .................................................................................. -0.3 V dc to +7.0 V dc
DC input voltage range (V
IN
) ................................................................................ -0.3 V dc to V
DD
+ 0.3 V dc
DC output voltage range (V
OUT
) ........................................................................... -0.3 V dc to V
DD
+ 0.3 V dc
DC input current, any one input (I
IN
).....................................................................
±10
mA
Latch-up immunity current (I
LU
) ............................................................................
±150
mA
Storage temperature range (T
STG
) ....................................................................... -65°C to +150°C
Lead temperature (soldering, 5 seconds) ............................................................ +300°C
Thermal resistance, junction-to-case (θ
JC
):
Case outline E and X, device type 01 ................................................................ See MIL-STD-1835
Case outline X, device types 02 and 03 ............................................................. 15.0°C/W
Junction temperature (T
J
) .................................................................................... +175°C
Maximum package power dissipation (P
D
):
Device type 01 ................................................................................................... 1.0 W
Device types 02 and 03 ..................................................................................... 3.3 W 4/
1.4 Recommended operating conditions. 2/ 3/
Supply voltage range (V
DD
):
Device type 01 ................................................................................................... +4.5 V dc to +5.5 V dc
Device types 02 and 03 ..................................................................................... +3.0 V dc to +5.5 V dc
Input voltage range (V
IN
) ...................................................................................... +0.0 V dc to V
DD
Output voltage range (V
OUT
)................................................................................. +0.0 V dc to V
DD
Case operating temperature range (T
C
) ............................................................... -55°C to +125°C
Maximum input rise and fall time at V
DD
= 4.5 V (t
r
, t
f
) ......................................... 1 ns/V 5/
1.5 Radiation features. 6/
Maximum total dose available:
6
Device type 01 (dose rate = 50 – 300 rads (Si)/s) ............................................ 1 x 10 Rads (Si) 7/
6
Device type 02 (effective dose rate = 1 rad (Si)/s) ........................................... 1 x 10 Rads (Si) 8/
5
Device type 03 (dose rate = 50 – 300 rads (Si)/s) ............................................ 5 x 10 Rads (Si) 7/
Single event phenomenon (SEP) effective:
Device type 01:
2
Effective LET, no upsets (see 4.4.4.4) ............................................................ ≤ 80 MeV-cm /mg 9/
2
Effective LET, no latch-up (see 4.4.4.4) .......................................................... ≤ 120 MeV-cm /mg 9/
Device types 02 and 03:
2
Effective LET, no upsets (see 4.4.4.4) ............................................................ ≤ 108 MeV-cm /mg 9/
2
Effective LET, no latch-up (see 4.4.4.4) .......................................................... ≤ 120 MeV-cm /mg 9/
9
Dose rate upset (20 ns pulse) ............................................................................ ≥ 1 x 10 Rads (Si)/s 9/ 10/
Dose rate latch-up ............................................................................................... None 9/
12
Dose rate survivability ....................................................................................... 1 x 10 Rads (Si)/s 9/
Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
2/ Unless otherwise specified, all voltages are referenced to V
SS.
3/ The limits for the parameters specified herein shall apply over the full specified V
DD
range and case temperature range
of -55°C to +125°C unless otherwise specified.
4/ Per MIL-STD-883 method 1012.1 section 3.4.1, P
D
(Package) = (T
J
(max) - T
C
(max)).
θ
JC
5/ Derate system propagation delays by difference in rise time to switch point for t
r
or t
f
>
1 ns/V.
6/ Radiation testing is performed on the standard evaluation circuit (SEC).
7/ Device types 01 and 03 are tested in accordance with MIL-STD-1019, condition A.
8/ Device type 02 is irradiated at dose rate = 50 - 300 rads (Si)/s in accordance with MIL-STD-883, method 1019,
condition A, and is guaranteed to a maximum total dose specified. The effective dose rate after extended room
temperature anneal = 1 rad (Si)/s per MIL-STD-883, method 1019, condition A, section 3.11.2. The total dose
specification for these devices only applies to a low dose rate environment.
9/ Limits are guaranteed by design or process, but not production tested unless specified by the customer through the
purchase order or contract.
10/ This limit is applicable for device type 01, 02, and 03 with V
DD
≥ 4.5 V. Device types 02 and 03 do not meet this limit at
V
DD
< 4.5 V..
1/
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
A
REVISION LEVEL
5962-96544
SHEET
F
3
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a
part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those
cited in the solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883
-
Test Method Standard Microcircuits.
Interface Standard Electronic Component Case Outlines.
MIL-STD-1835 -
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 -
MIL-HDBK-780 -
List of Standard Microcircuit Drawings.
Standard Microcircuit Drawings.
(Copies of these documents are available online at
https://assist.dla.mil/quicksearch/
or from the Standardization Document
Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein.
Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation or contract.
ASTM INTERNATIONAL (ASTM)
ASTM F1192 - Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion
Irradiation of Semiconductor Devices.
(Copies of this document is available online at
https://www.astm.org/
or from ASTM International, P. O. Box C700,
100 Barr Harbor Drive, West Conshohocken, PA 19428-2959).
JEDEC – SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC)
JESD 20 - Standard for Description of 54/74ACXXXX and 54/74ACTXXXX Advanced High-Speed CMOS Devices.
(Copies of these documents are available online at
http://www.jedec.org/
or from JEDEC – Solid State Technology
Association, 3103 North 10th Street, Suite 240–S, Arlington, VA 22201-2701.)
2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
A
REVISION LEVEL
5962-96544
SHEET
F
4
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein.
3.1.1 Microcircuit die. For the requirements of microcircuit die, see appendix A to this document.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in
MIL-PRF-38535 and herein for device classes Q and V.
3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.
3.2.3 Truth table. The truth table shall be as specified on figure 2.
3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3.
3.2.5 Switching waveforms and test circuits. The switching waveforms and test circuits shall be as specified on figure 4.
3.2.6 Irradiation test connections. The irradiation test connections shall be maintained by the manufacturer under document
revision level control and shall be made available to the preparing and acquiring activity upon request.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the
full case operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The
electrical tests for each subgroup are described in table IA.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer
has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be
marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in
MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). The certificate of compliance
submitted to DLA Land and Maritime -VA prior to listing as an approved source of supply for this drawing shall affirm that the
manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for
device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
A
REVISION LEVEL
5962-96544
SHEET
F
5
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参数对比
与5962H9654401QEA相近的元器件有:5962H9654401VEA、5962H9654401VEC、5962H9654401Q9A、5962H9654401QEC、5962H9654401V9A。描述及对比如下:
型号 5962H9654401QEA 5962H9654401VEA 5962H9654401VEC 5962H9654401Q9A 5962H9654401QEC 5962H9654401V9A
描述 Decoder/Driver, AC Series, Inverted Output, CMOS, CDIP16, CERAMIC, DIP-16 Decoder/Driver, AC Series, Inverted Output, CMOS, CDIP16, CERAMIC, DIP-16 Decoder/Driver, AC Series, Inverted Output, CMOS, CDIP16, CERAMIC, DIP-16 Decoder/Driver, AC Series, Inverted Output, CMOS, DIE-16 Decoder/Driver, AC Series, Inverted Output, CMOS, CDIP16, CERAMIC, DIP-16 Decoder/Driver, AC Series, Inverted Output, CMOS, DIE-16
包装说明 DIP, DIP16,.3 DIP, DIP16,.3 DIP, DIP16,.3 DIE, DIE OR CHIP DIP, DIP16,.3 DIE, DIE OR CHIP
Reach Compliance Code unknown unknown unknown unknown unknown unknown
ECCN代码 3A001.A.1.A 3A001.A.1.A 3A001.A.1.A 3A001.A.1.A 3A001.A.1.A 3A001.A.1.A
系列 AC AC AC AC AC AC
输入调节 STANDARD STANDARD STANDARD STANDARD STANDARD STANDARD
JESD-30 代码 R-GDIP-T16 R-GDIP-T16 R-GDIP-T16 R-XUUC-N16 R-GDIP-T16 R-XUUC-N16
JESD-609代码 e0 e0 e4 e0 e4 e0
负载电容(CL) 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF
逻辑集成电路类型 OTHER DECODER/DRIVER OTHER DECODER/DRIVER OTHER DECODER/DRIVER OTHER DECODER/DRIVER OTHER DECODER/DRIVER OTHER DECODER/DRIVER
最大I(ol) 0.008 A 0.008 A 0.008 A 0.008 A 0.008 A 0.008 A
功能数量 1 1 1 1 1 1
端子数量 16 16 16 16 16 16
最高工作温度 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C
最低工作温度 -55 °C -55 °C -55 °C -55 °C -55 °C -55 °C
输出极性 INVERTED INVERTED INVERTED INVERTED INVERTED INVERTED
封装主体材料 CERAMIC, GLASS-SEALED CERAMIC, GLASS-SEALED CERAMIC, GLASS-SEALED UNSPECIFIED CERAMIC, GLASS-SEALED UNSPECIFIED
封装代码 DIP DIP DIP DIE DIP DIE
封装等效代码 DIP16,.3 DIP16,.3 DIP16,.3 DIE OR CHIP DIP16,.3 DIE OR CHIP
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 IN-LINE IN-LINE IN-LINE UNCASED CHIP IN-LINE UNCASED CHIP
电源 5 V 5 V 5 V 5 V 5 V 5 V
Prop。Delay @ Nom-Sup 17 ns 17 ns 17 ns 17 ns 17 ns 17 ns
传播延迟(tpd) 15 ns 15 ns 15 ns 15 ns 15 ns 15 ns
认证状态 Qualified Qualified Qualified Qualified Qualified Qualified
筛选级别 MIL-PRF-38535 Class Q MIL-PRF-38535 Class V MIL-PRF-38535 Class V MIL-PRF-38535 Class Q MIL-PRF-38535 Class Q MIL-PRF-38535 Class V
最大供电电压 (Vsup) 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V
最小供电电压 (Vsup) 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V
标称供电电压 (Vsup) 5 V 5 V 5 V 5 V 5 V 5 V
表面贴装 NO NO NO YES NO YES
技术 CMOS CMOS CMOS CMOS CMOS CMOS
温度等级 MILITARY MILITARY MILITARY MILITARY MILITARY MILITARY
端子面层 TIN LEAD TIN LEAD GOLD TIN LEAD GOLD TIN LEAD
端子形式 THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE NO LEAD THROUGH-HOLE NO LEAD
端子位置 DUAL DUAL DUAL UPPER DUAL UPPER
总剂量 1M Rad(Si) V 1M Rad(Si) V 1M Rad(Si) V 1M Rad(Si) V 1M Rad(Si) V 1M Rad(Si) V
Base Number Matches 1 1 1 1 1 1
端子节距 2.54 mm 2.54 mm 2.54 mm - 2.54 mm -
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