Standard Products
UT8R1M39 40Megabit SRAM MCM
UT8R2M39 80Megabit SRAM MCM
UT8R4M39 160Megabit SRAM MCM
Data Sheet
June 2015
The most important thing we build is trust
FEATURES
20ns Read, 10ns Write maximum access times available
Functionally compatible with traditional 1M, 2M, or 4M x
39 SRAM devices
CMOS compatible input and output levels, three-state
bidirectional data bus
- I/O Voltages 2.3V to 3.6V, 1.7V to 2.0V core
Available densities:
- UT8R1M39: 40, 894, 464 bits
- UT8R2M39: 81, 788, 928 bits
- UT8R4M39: 163, 577, 856 bits
Operational Environment:
- Total-dose: 100 krad(Si)
- SEL Immune: <110 MeV-cm
2
/mg
- SEU error rate = 7.3x10
-7
errors/bit-day assuming
geosynchronous orbit, Adam’s 90% worst environment.
Packaging options:
- 132-lead side-brazed dual cavity ceramic quad flatpack
Standard Microelectronics Drawing:
- UT8R1M39: 5962-10205
- QML Q, Q+ and V compliant
- UT8R2M39: 5962-10206
- QML Q, Q+, and Vcompliant
- UT8R4M39: 5962-10207
- QML Q and Q+ compliant part
INTRODUCTION
The UT8R1M39, UT8R2M39, and UT8R4M39 are high
performance CMOS static RAM multichip modules (MCMs)
organized as two, four or eight individual 524,288 words x 39
bits dice respectively. Easy memory expansion is provided by
active LOW chip enables (En), an active LOW output enable
(G), and three-state drivers. This device has a power-down
feature that reduces power consumption by more than 90% when
deselected.
Writing to the device is accomplished by driving one of the chip
enable (En) inputs LOW and the write enable (W) input LOW.
Data on the 39 I/O pins (DQ0 through DQ38) is then written into
the location specified on the address pins (A0 through A18).
Reading from the device is accomplished by driving one of the
chip enables (En) and output enable (G) LOW while driving
write enable (W) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
Note:
Only one En pin may be active at any time.
The 39 input/output pins (DQ0 through DQ38) are placed in a
high impedance state when the device is deselected (En HIGH),
the outputs are disabled (G HIGH), or during a write operation
(En LOW, W LOW).
Figure 1. Block Diagram
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TOP_DQ34
A11
A12
A13
VSS
NC
NC
NC
VDD2
NC
VDD1
E7# (NC)
E5# (NC)
E3# (NC)
E1#
VDD1
G#
VSS
E2#
E4# (NC)
E6# (NC)
E8# (NC)
VDD1
VDD2
VSS
VSS
NC
NC
VSS
A14
A15
A16
BOT_DQ34
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
TOP_DQ38
BOT_DQ38
DQ0
DQ1
DQ2
DQ3
VDD2
VSS
DQ4
DQ5
DQ6
DQ7
VDD1
VSS
NC
VDD2
NC
VDD2
NC
VSS
VDD1
DQ8
DQ9
DQ10
DQ11
VSS
VDD2
DQ12
DQ13
DQ14
DQ15
TOP_DQ32
TOP_DQ33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
132
131
130
129
128
127
126
125
124
123
1
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
BOT_DQ37
TOP_DQ37
A0
A1
A2
A3
VDD1
VSS
A4
A5
A17
NC
VDD1
NC
NC
VSS
NC
VDD1
NC
NC
VDD1
NC
A18
W#
A6
VSS
VDD1
A7
A8
A9
A10
TOP_DQ36
BOT_DQ36
40M /80M/ 160M
2-, 4-, 8- Die
SRAM MCM Module
(0.90” Square, 132-lead Side-Brazed Dual Cavity
Ceramic Flatpack)
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
TOP_DQ35
BOT_DQ35
DQ16
DQ17
DQ18
DQ19
VDD2
VSS
DQ20
DQ21
DQ22
DQ23
VDD1
VSS
NC
VDD2
NC
VDD2
NC
VSS
VDD1
DQ24
DQ25
DQ26
DQ27
VSS
VDD2
DQ28
DQ29
DQ30
DQ31
BOT_DQ32
BOT_DQ33
Notes:
1. NC=Pins are not connected on die.
2. (NC) = Depending on product version, the pin may be either an enable signal as named or NC.
3. Each TOP and BOT signal for DQ38 through DQ32 must be externally connected
by user.
Figure 2. Pin Diagram
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Table 1. Device Option: Signal and Pin Description
Package Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
UT8R1M39
Signal Name
TOP_DQ38
BOT_DQ38
DQ0
DQ1
DQ2
DQ3
VDD2
VSS
DQ4
DQ5
DQ6
DQ7
VDD1
VSS
NC
VDD2
NC
VDD2
NC
VSS
VDD1
DQ8
DQ9
DQ10
DQ11
VSS
VDD2
DQ12
DQ13
UT8R2M39
Signal Name
TOP_DQ38
BOT_DQ38
DQ0
DQ1
DQ2
DQ3
VDD2
VSS
DQ4
DQ5
DQ6
DQ7
VDD1
VSS
NC
VDD2
NC
VDD2
NC
VSS
VDD1
DQ8
DQ9
DQ10
DQ11
VSS
VDD2
DQ12
DQ13
UT8R4M39
Signal Name
TOP_DQ38
BOT_DQ38
DQ0
DQ1
DQ2
DQ3
VDD2
VSS
DQ4
DQ5
DQ6
DQ7
VDD1
VSS
NC
VDD2
NC
VDD2
NC
VSS
VDD1
DQ8
DQ9
DQ10
DQ11
VSS
VDD2
DQ12
DQ13
Device Pin
Description
Data I/O
1
Data I/O
1
Data I/O
Data I/O
Data I/O
Data I/O
PWR
PWR
Data I/O
Data I/O
Data I/O
Data I/O
PWR
PWR
NC
PWR
NC
PWR
NC
PWR
PWR
Data I/O
Data I/O
Data I/O
Data I/O
PWR
PWR
Data I/O
Data I/O
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Table 1. Device Option: Signal and Pin Description
Package Pin
Number
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
UT8R1M39
Signal Name
DQ14
DQ15
TOP_DQ32
TOP_DQ33
TOP_DQ34
A11
A12
A13
VSS
NC
NC
NC
VDD2
NC
VDD1
NC
NC
NC
E1#
VDD1
G#
VSS
E2#
NC
NC
NC
VDD1
VDD2
VSS
VSS
NC
UT8R2M39
Signal Name
DQ14
DQ15
TOP_DQ32
TOP_DQ33
TOP_DQ34
A11
A12
A13
VSS
NC
NC
NC
VDD2
NC
VDD1
NC
NC
E3#
E1#
VDD1
G#
VSS
E2#
E4#
NC
NC
VDD1
VDD2
VSS
VSS
NC
UT8R4M39
Signal Name
DQ14
DQ15
TOP_DQ32
TOP_DQ33
TOP_DQ34
A11
A12
A13
VSS
NC
NC
NC
VDD2
Nc
VDD1
E7#
E5#
E3#
E1#
VDD1
G#
VSS
E2#
E4#
E6#
E8#
VDD1
VDD2
VSS
VSS
NC
Device Pin
Description
Data I/O
Data I/O
Data I/O
1
Data I/O
1
Data I/O
1
ADDRESS INPUT
ADDRESS INPUT
ADDRESS INPUT
PWR
NC
NC
NC
PWR
NC
PWR
CONTROL INPUT
2
CONTROL INPUT
2
CONTROL INPUT
2
CONTROL INPUT
PWR
CONTROL INPUT
PWR
CONTROL INPUT
CONTROL INPUT
2
CONTROL INPUT
2
CONTROL INPUT
2
PWR
PWR
PWR
PWR
NC
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Table 1. Device Option: Signal and Pin Description
Package Pin
Number
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
UT8R1M39
Signal Name
NC
VSS
A14
A15
A16
BOT_DQ34
BOT_DQ33
BOT_DQ32
DQ31
DQ30
DQ29
DQ28
VDD2
VSS
DQ27
DQ26
DQ25
DQ24
VDD1
VSS
NC
VDD2
NC
VDD2
NC
VSS
VDD1
DQ23
DQ22
DQ21
UT8R2M39
Signal Name
NC
VSS
A14
A15
A16
BOT_DQ34
BOT_DQ33
BOT_DQ32
DQ31
DQ30
DQ29
DQ28
VDD2
VSS
DQ27
DQ26
DQ25
DQ24
VDD1
VSS
NC
VDD2
NC
VDD2
NC
VSS
VDD1
DQ23
DQ22
DQ21
UT8R4M39
Signal Name
NC
VSS
A14
A15
A16
BOT_DQ34
BOT_DQ33
BOT_DQ32
DQ31
DQ30
DQ29
DQ28
VDD2
VSS
DQ27
DQ26
DQ25
DQ24
VDD1
VSS
NC
VDD2
NC
VDD2
NC
VSS
VDD1
DQ23
DQ22
DQ21
Device Pin
Description
NC
PWR
ADDRESS INPUT
ADDRESS INPUT
ADDRESS INPUT
Data I/O
1
Data I/O
1
Data I/O
1
Data I/O
Data I/O
Data I/O
Data I/O
PWR
1
PWR
Data I/O
Data I/O
Data I/O
Data I/O
PWR
PWR
NC
PWR
NC
PWR
NC
PWR
PWR
Data I/O
Data I/O
Data I/O
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