1.0 I
NTRODUCTION
The monolithic SµMMIT provides the system designer with an
intelligent solution to MIL-STD-1553 multiplexed serial data
bus design problems. The SµMMIT is a single-chip device that
implements all three of the defined MIL-STD-1553 functions -
Remote Terminal, Bus Controller, and Monitor. Operating either
autonomously or with a tightly coupled host, the SµMMIT will
solve a wide range of MIL-STD-1553 interface problems. A
powerful RISC processing unit provides automatic message
handling, message status, general status, and interrupt
information. The register-based interface architecture provides
many programmable functions as well as extensive information
pertinent to device maintenance. In either of the three operating
modes, the SµMMIT can access up to 64K x 16 of external
memory (65,536 x 16).
The SµMMIT (which derives its name from serial,
µ−coded,
monolithic, multi-mode, intelligent, terminal) is a powerful
asset to a system designer solving the MIL-STD-1553 problem.
1.1 Remote Terminal Features
The SµMMIT Remote Terminal (SRT) conforms to the
requirements of MIL-STD-1553B, Notice II. In addition to
meeting the requirements of the standard, the SRT has an
extensive list of flexible features to meet any MIL-STD-1553
interface requirement.
1.1.1 Indexing
The SRT can buffer up to 256 receive messages on a subaddress-
by-subaddress basis. Upon reception of the specified number of
messages, the SRT can generate an interrupt by signaling either
the host or subsystem that data is ready for processing. The
indexing feature is commonly used to implement bulk data
transfer algorithms.
1.1.2 Buffer Ping-Pong
To support the transfer of periodic data, double buffering
schemes are often incorporated into remote terminal designs.
Periodic data transfer incorporates the use of two data buffers
per subaddress. The remote terminal processes messages
(receive or transmit) via the designated primary buffer. The host
or subsystem uses the secondary buffer to collect new data for
transmission or processing data received during the defined time
interval. Upon completion of the defined interval, the remote
terminal will switch the primary and secondary data buffers (i.e.,
ping-pong). The SRT supports ping-pong buffering via a user-
selected ping-pong architecture consisting of dual subaddress
data pointers.
1.1.3 Circular Buffers
SµMMIT circular buffer modes simplify the software service
of remote terminals implementing bulk or periodic data
transfers. The SµMMIT architecture allows the user to select
one of two circular buffer modes. The user selects the preferred
mode, at start-up, by writing to Control Register bits.
1.1.4 Internal Illegalization
An internal 256-bit (16 x 16) RAM allows for the illegalization
of all mode codes and subaddresses. The illegalization RAM is
accessed at the beginning of message processing to determine
if the valid command is prohibited. To eliminate host or
subsystem overhead, the SµΜΜIT can initialize the 256-bit
illegalization RAM during the auto-initialization sequence.
1.1.5 Broadcast
Designed to meet the requirements of MIL-STD-1553B Notice
II, the SRT can store all data associated with a broadcast
command in separate memory from non-broadcast commands.
This feature is user-selected via the Descriptor Control word
and internal Control Register.
1.1.6 Interrupt History
A programmable interrupt structure allows the host or
subsystem the flexibility to enter 16 interrupts into a 32-word
buffer before service. This feature allows the logging of multiple
interrupts if immediate service is restricted. The interrupt
structure enters an Interrupt Information Word (IIW) and an
Interrupt Address Word (IAW) indicating what subaddress or
command block generated the interrupt. All modes of operation
support interrupt logging.
1.1.7 Message Information
The SRT generates a Message Information Word and time-tag
(16-bit) for all transacted messages. This information is written
into memory along with message data words. The Message
Information Word contains word count, message errors, and
message type information.
1.2 Bus Controller Features
The SµMMIT Bus Controller (SBC) is a powerful MIL-STD-
1553 bus controller developed to meet the requirements of
multi-frame processing with low host overhead. User-defined
decision making allows the SBC to operate autonomously from
the host until a designated event or series of events has taken
place.
SµMMIT FAMILY - 1
1.2.1 Multiple Message Processing
The SBC architecture allows the chaining of multiple MIL-
STD-1553 commands into major and minor frames depending
on the application. This feature allows the host to structure
message frames that perform independent tasks such as periodic
data transfer, service requests, and bus diagnostics (initiate
BIT). The SBC uses a simple opcode scheme to control the
command block flow.
1.2.2 Message Scheduling
The SBC allows host entry of data to control the time between
messages. This feature is useful when the BC has to perform
periodic message transactions with multiple remote terminals.
1.2.3 Polling
The host instructs the SBC to interrogate the status word
response of remote terminals to determine if any SBC action is
required. The SBC can detect the assertion of status word bits
and generate interrupts or branch to a new message frame.
Polling is useful if the application requires control of message
frame flow as a function of remote terminal response.
1.2.4 Automatic Retry
The SBC can automatically retry a message on busy, message
error, or other status word bit response. If enabled, the SBC can
retry up to four times, per command block, on the primary bus
or alternate bus.
1.3 Monitor Terminal Features
The SµMMIT Monitor Terminal (SMT) is a full-featured MIL-
STD-1553B bus monitor designed to monitor all or selected
remote terminals on the bus. Requiring little host intervention,
the SMT will monitor selected remote terminals until a pre-
defined message count is reached. Generation of an interrupt
alerts the host that SMT service is required.
1.3.1 Message Information
Each message transaction generates a Message Information
Word. This information helps determine message validity and
remote terminal health. The Message Information Word is
stored in external memory along with message data words.
1.4 Remote Terminal/Monitor Terminal Feature
For those applications that require the SMT to transfer or receive
information, the SµMMIT is configured as both a remote
terminal (SRT) and monitor (SMT). This feature allows the
SMT to communicate on the bus as a RT, and monitor bus
activity. Configuration as both SMT and SRT precludes the
SMT from monitoring its own remote terminal address.
1.5 Protocol Definition
For maximum flexibility, the SµΜΜIT has been designed to
operate in many different systems which use various protocols.
Specifically, two of the protocols that the SµMMIT may
interface are MIL-STD-1553A and MIL-STD-1553B. To meet
these protocols, the SµΜΜIT may be configured through an
external pin or through control register bits.
1.6 SµMMIT LXE/DXE & XTE Transceivers
Internal monolithic transceivers are complete transmitter and
receiver pairs for MIL-STD-1553A and 1553B applications.
The receiver section accepts biphase-modulated Manchester II
bipolar data from MIL-STD-1553 data bus and produces TTL-
level signal data at its internal RXOUT and RXOUT outputs.
The transmitter section accepts biphase TTL-level signal data
at its internal TXIN and TXIN inputs and produces MIL-STD-
1553 data signals. The transmitter’s output voltage is typically
10V
P-P,LL
for the SµMMIT XTE5 & DXE and 42V
P-P,LL
for
the SµMMIT XTE15, XTE12 & LXE.
1.7 SµMMIT XTE Memory
The SµMMIT XTE contains 512 Kbits of internal memory for
message processing. Internal logic generates a RDY signal for
the subsystem interface. The internal memory is memory
mapped.
SµMMIT FAMILY - 2
SµMMIT F
EATURES
r
Comprehensive MIL-STD-1553 dual redundant Bus
Controller (BC), Remote Terminal (RT), and Monitor
Terminal (MT)
r
MIL-STD-1553B, Notice II RT
- Internal command illegalization in the RT mode
- 16-bit read/write time-tag with user-defined resolution
- Subaddress data buffering
r
Simultaneous RT/MT mode of operation
r
Flexible BC architecture designed to off-load the host
computer
- Minor frame timing
- Efficient command block flow statements
(Branch, Go To, Call)
- Status word polling
- Programmable retries
r
Programmable interrupt architecture with automatic
interrupt logging available in all modes
CONFIGURATION
CONTROL INPUTS
OUTPUT MULTIPLEXOR AND
SELF-TEST WRAP-AROUND LOGIC
STATUS
SIGNALS
r
Autonomous operation in all three modes of operation
- Ideal for low cost remote terminals
r
Built-In Test capability
r
Supports IEEE Standard 1149.1 (JTAG)
r
Radiation-hardened option available
r
Flexible packaging offering:
- 84-pin pingrid array (PGA)(not available RadHard)
- 84-lead flatpack
- 132-lead flatpack (not available RadHard)
r
Standard Microcircuit Drawing 5962-92118 available
- QML Q & V compliant
CHANNEL A
DECODER
BC CONTROLLER
RT CONTROLLER
MT CONTROLLER
DECODER
CHANNEL B
ENCODER
INSTRUCTION
MEMORY
BUILT-IN
TEST
CLOCK and
RESET LOGIC
REGISTER FILE
DATA
(32 x 16)
TRANSFER
MESSAGE BUFFER
LOGIC
INTERRUPT
CONTROL
BOUNDARY
SCAN
CONTROL
MASTER RESET
AND
CLOCKS
ADDRESS/DATA
AND
CONTROL SIGNALS
INTERRUPT
OUTPUTS
Figure 1. UT69151 SµMMIT Block Diagram
SµMMIT FAMILY - 3
LXE/DXE F
EATURES
r
Comprehensive MIL-STD-1553 dual redundant Bus
Controller(BC), Remote Terminal (RT), and Monitor
Terminal (MT) with integrated bus transceivers
r
MIL-STD-1553B, Notice II RT
- Internal command illegalization in the RT mode
- 16-bit read/write time-tag with user-defined resolution
- Subaddress data buffering
r
Simultaneous RT/MT mode of operation
r
Flexible BC architecture designed to off-load the host
computer
- Minor frame timing
- Efficient command block flow statements
(Branch, Go To, Call)
- Status word polling
- Programmable retries
r
Programmable interrupt architecture with automatic
interrupt logging available in all modes
r
Autonomous operation in all three modes of operation
- Ideal for low cost remote terminals
r
Built-In Test capability
r
Supports IEEE Standard 1149.1 (JTAG)
r
Flexible power supply configurations
- +5-volt only operation
- -15-volt and 5-volt operation
- -12-volt and 5-volt operation
r
Radiation-hardened option available
r
Flexible packaging offering:
- 96-pin pingrid array (PGA) (not available RadHard)
- 100-lead flatpack
- Complete interface in 1.4 in
2
r
Standard Microcircuit Drawing 5962-94663
- QML Q and V compliant
MODE
STATUS
JTAG
CHA
TRANSCEIVER
CHA
ADDRESS
DATA
SµMMIT
CHB
TRANSCEIVER
INTERFACE
CONTROL
INTERRUPTS
CHB
REMOTE
TERMINAL
ADDRESS
AUTO-INIT
BUS
Figure 2. UT69151 SµMMIT LXE/DXE Block Diagram
SµMMIT FAMILY - 4
XTE F
EATURES
r
Comprehensive MIL-STD-1553 dual redundant Bus
Controller (BC), Remote Terminal (RT), and Monitor
Terminal (MT) with integrated bus transceivers, Memory,
and Memory Management Unit (MMU)
r
MIL-STD-1553B, Notice II RT
- Internal command illegalization in the RT mode
- 16-bit read/write time-tag with user-defined resolution
- Subaddress data buffering
r
Simultaneous RT/MT mode of operation
r
Flexible BC architecture designed to off-load the host
computer
- Minor frame timing
- Efficient command block flow statements
(Branch, Go To, Call)
- Status word polling
- Programmable retries
r
Programmable interrupt architecture with automatic
interrupt logging available in all modes
r
Autonomous operation in all three modes of operation
- External initialization bus
- Ideal for low cost remote terminals
r
Internal Memory Management Unit (MMU) interfaces host
subsystem to 512Kbit SRAM
- Wait state and zero-wait state configurations
r
Built-In Test capability
r
Supports IEEE Standard 1149.1 (JTAG)
r
Flexible power supply configurations
- +5-volt only operation
- -15-volt and 5-volt operation
- -12-volt and 5-volt operation
r
Flexible packaging offering:
- 139-pin pingrid array (PGA)
- 140-lead flatpack
- Complete interface in 1.9 in
2
r
Standard Microcircuit Drawing 5962-94758
-
QML Q and V compliant
MODE
STATUS
JTAG
INTERRUPTS
CHA
TRANSCEIVER
CHA
SµMMIT
Protocol
Handler
CHB
TRANSCEIVER
CHB
Memory
MMU
INTERFACE
CONTROL
AUTO-INIT BUS
DATA
ADDRESS
REMOTE
TERMINAL
ADDRESS
MEMORY
Figure 3. UT69151 SµMMIT XTE Block Diagram
SµMMIT FAMILY - 5
嵌入式系统
