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5962R9569002VCC

QUAD OP-AMP, 3000uV OFFSET-MAX, 8MHz BAND WIDTH, CDIP14, ROHS COMPLIANT, HERMETIC SEALED, METAL SEALED, CERAMIC, SBDIP-14

器件类别:模拟混合信号IC    放大器电路   

厂商名称:Renesas(瑞萨电子)

厂商官网:https://www.renesas.com/

器件标准:

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器件参数
参数名称
属性值
是否Rohs认证
符合
厂商名称
Renesas(瑞萨电子)
包装说明
DIP,
Reach Compliance Code
compliant
ECCN代码
USML XV(E)
放大器类型
OPERATIONAL AMPLIFIER
最大输入失调电压
3000 µV
JESD-30 代码
R-CDIP-T14
JESD-609代码
e4
长度
19.94 mm
功能数量
4
端子数量
14
最高工作温度
125 °C
最低工作温度
-55 °C
封装主体材料
CERAMIC, METAL-SEALED COFIRED
封装代码
DIP
封装形状
RECTANGULAR
封装形式
IN-LINE
峰值回流温度(摄氏度)
NOT SPECIFIED
认证状态
Not Qualified
筛选级别
MIL-PRF-38535 Class V
座面最大高度
5.08 mm
标称压摆率
2 V/us
表面贴装
NO
技术
BIPOLAR
温度等级
MILITARY
端子面层
Gold (Au)
端子形式
THROUGH-HOLE
端子节距
2.54 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
NOT SPECIFIED
总剂量
100k Rad(Si) V
标称均一增益带宽
8000 kHz
宽度
7.62 mm
文档预览
DATASHEET
Radiation Hardened, Low Noise Quad Operational
Amplifiers
HS-5104ARH, HS-5104AEH
The HS-5104ARH, HS-5104AEH are radiation hardened,
monolithic quad operational amplifiers that provide highly
reliable performance in harsh radiation environments.
Excellent noise characteristics coupled with a unique array of
dynamic specifications make these amplifiers well-suited for a
variety of satellite system applications. Dielectrically isolated,
bipolar processing makes these devices immune to Single
Event Latch-Up.
The HS-5104ARH, HS-5104AEH show almost no change in offset
voltage after exposure to 100kRAD(Si) gamma radiation, with
only a minor increase in current. Complementing these
specifications is a post radiation open loop gain in excess of 40k.
These quad operational amplifiers are available in an industry
standard pinout, allowing for immediate interchangeability
with most other quad operational amplifiers.
Features
• Electrically screened to SMD #
5962-95690
• QML qualified per MIL-PRF-38535 requirements
• Radiation environment
- High dose rate (50-300rad(Si)/s). . . . . . . . . . . 100krad(Si)
- Low dose rate (0.01rad(Si)/s) . . . . . . . . . . . . . . .50krad(Si)
• No latch-up, dielectrically isolated device islands
• Low noise
- At 1kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3nV/Hz (Typ)
- At 1kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6pA/Hz (Typ)
• Low offset voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.0mV (Max)
• High slew rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0V/µs (Typ)
• Gain bandwidth product . . . . . . . . . . . . . . . . . . . .8.0MHz (Typ)
Applications
• High Q, active filters
• Voltage regulators
• Integrators
• Signal generators
• Voltage references
• Space environment
Ordering Information
ORDERING/SMD NUMBER
5962R9569001VXC
5962R9569002VXC
5962R9569001VCC
5962R9569002VCC
5962R9569001V9A
5962R9569002V9A
HS1-5104ARH/PROTO
HS0-5104ARH/SAMPLE
HS9-5104ARH/PROTO
INTERNAL
MKT. NUMBER
(NOTE 1 )
HS9-5104ARH-Q
HS9-5104AEH-Q
HS1-5104ARH-Q
HS1-5104AEH-Q
HS0-5104ARH-Q
HS0-5104AEH-Q
HS1-5104ARH/PROTO
HS0-5104ARH/SAMPLE
HS9-5104ARH/PROTO
TEMP. RANGE
(°C)
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
HS9-5104ARH/PROTO
HS1-5104ARH/PROTO
PART
MARKING
Q 5962R95 69001VXC
Q 5962R95 69002VXC
Q 5962R95 69001VCC
Q 5962R95 69002VCC
PACKAGE
(RoHS Compliant)
(NOTE 2)
14 Ld Flatpack
14 Ld Flatpack
14 Ld SBDIP
14 Ld SBDIP
Die
Die
14 Ld SBDIP
Die
14 Ld Flatpack
K14.A
D14.3
PKG. DWG. #
K14.A
K14.A
D14.3
D14.3
1. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed in
the“Ordering Information” table must be used when ordering.
2. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with
both SnPb and Pb-free soldering operations.
July 12, 2013
FN3025.5
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Copyright Intersil Americas LLC 2002, 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
HS-5104ARH, HS-5104AEH
Pin Configuration
HS1-5104ARH, HS1-5104AEH
(14 LD SBDIP)
TOP VIEW
OUT 1
-IN1
+IN1
V+
+IN2
-IN2
OUT 2
1
2
3
4
5
6
7
14
13
12
11
10
9
8
OUT 4
-IN4
+IN4
V-
+IN3
-IN3
OUT 3
HS9-5104ARH, HS9-5104AEH
(14 LD FLATPACK)
TOP VIEW
OUT 1
-IN1
+IN1
V+
+IN2
-IN2
OUT 2
1
2
3
4
5
6
7
14
13
12
11
10
9
8
OUT 4
-IN4
+IN4
V-
+IN3
-IN3
OUT 3
Irradiation Circuit
Burn In Circuit
1
14
1
+15V
R1
+
+V
-15V
(ONE OF FOUR)
C1
D1
R2
2
3
4
5
6
7
-
+
4
+
-
13
12
11
R4
-V
R3
D2
C2
-
2
+
3
+
10
9
8
-
-
NOTES:
3. +V = 15V
4. -V = -15V
5. Group E Sample Size = 4 Die Per Wafer
NOTES:
6. R1 = R2 = R3 = R4 = 1MW, 5%, 1/4W (Min)
7. C1 = C2 = 0.01µF/Socket (Min) or 0.1µF/Row (Min)
8. D1 = D2 = IN4002 or Equivalent/Board
9. |(V+) - (V-)| = 31V ±1V
2
FN3025.5
July 12, 2013
HS-5104ARH, HS-5104AEH
Die Characteristics
DIE DIMENSIONS:
95mils x 99mils x 19 mils ±1mils
(2420µm x 2530µm x 483µm ±25.4µm)
Backside Finish:
Silicon
INTERFACE MATERIALS:
Glassivation:
Type: Nitride (SI3N4) over Silox (SIO2, 5% Phos.)
Silox Thickness: 12k
Å
±2k
Å
Nitride Thickness: 3.5k
Å
±1.5k
Å
Top Metallization:
Type: Al, 1% Cu
Thickness: 16k
Å
±2k
Å
Substrate:
Bipolar Dielectric Isolation
ASSEMBLY RELATED INFORMATION:
Substrate Potential (Powered Up):
Unbiased
ADDITIONAL INFORMATION:
Worst Case Current Density:
<2.0 x 10
5
A/cm
2
Transistor Count:
175
Metallization Mask Layout
HS-5104ARH, HS-5104AEH
+IN2
V+
+IN1
-IN2
-IN1
OUT2
OUT3
OUT1
OUT4
-IN3
-IN4
+IN3
V-
+IN4
For additional products, see
www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at
www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see
www.intersil.com
3
FN3025.5
July 12, 2013
HS-5104ARH, HS-5104AEH
Ceramic Metal Seal Flatpack Packages (Flatpack)
A
K14.A
MIL-STD-1835 CDFP3-F14 (F-2A, CONFIGURATION B)
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
INCHES
SYMBOL
MIN
0.045
0.015
0.015
0.004
0.004
-
0.235
-
0.125
0.030
0.008
0.270
0.026
0.005
-
14
MAX
0.115
0.022
0.019
0.009
0.006
0.390
0.260
0.290
-
-
0.015
0.370
0.045
-
0.0015
A
b
b1
c
c1
D
MILLIMETERS
MIN
1.14
0.38
0.38
0.10
0.10
-
5.97
-
3.18
0.76
1.27 BSC
0.20
6.86
0.66
0.13
-
14
0.38
9.40
1.14
-
0.04
MAX
2.92
0.56
0.48
0.23
0.15
9.91
6.60
7.11
-
-
NOTES
-
-
-
-
-
3
-
3
-
7
-
2
-
8
6
-
-
Rev. 0 5/18/94
e
PIN NO. 1
ID AREA
A
-A-
-B-
D
S1
b
E1
0.004 M
Q
A
-C-
-H-
L
E3
SEATING AND
BASE PLANE
c1
LEAD FINISH
E2
E3
L
H A-B S
D S
E
0.036 M
H A-B S
C
-D-
D S
E
E1
E2
E3
e
k
L
Q
S1
M
N
0.050 BSC
BASE
METAL
b1
M
M
(b)
SECTION A-A
(c)
NOTES:
1. Index area: A notch or a pin one identification mark shall be located
adjacent to pin one and shall be located within the shaded area
shown. The manufacturer’s identification shall not be used as a pin
one identification mark. Alternately, a tab (dimension k) may be
used to identify pin one.
2. If a pin one identification mark is used in addition to a tab, the limits
of dimension k do not apply.
3. This dimension allows for off-center lid, meniscus, and glass over-
run.
4. Dimensions b1 and c1 apply to lead base metal only. Dimension M
applies to lead plating and finish thickness. The maximum limits of
lead dimensions b and c or M shall be measured at the centroid of
the finished lead surfaces, when solder dip or tin plate lead finish is
applied.
5. N is the maximum number of terminal positions.
6. Measure dimension S1 at all four corners.
7. For bottom-brazed lead packages, no organic or polymeric materi-
als shall be molded to the bottom of the package to cover the leads.
8. Dimension Q shall be measured at the point of exit (beyond the me-
niscus) of the lead from the body. Dimension Q minimum shall be
reduced by 0.0015 inch (0.038mm) maximum when solder dip lead
finish is applied.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
4
FN3025.5
July 12, 2013
HS-5104ARH, HS-5104AEH
Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
c1
-A-
-D-
BASE
METAL
M
-B-
bbb S C A - B S
BASE
PLANE
SEATING
PLANE
S1
b2
b
A A
D
S2
-C-
Q
A
L
D S
b1
M
(b)
SECTION A-A
(c)
LEAD FINISH
D14.3
MIL-STD-1835 CDIP2-T14 (D-1, CONFIGURATION C)
14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
INCHES
SYMBOL
A
b
b1
b2
b3
c
c1
D
E
e
eA
eA/2
L
Q
S1
S2
MIN
-
0.014
0.014
0.045
0.023
0.008
0.008
-
0.220
MAX
0.200
0.026
0.023
0.065
0.045
0.018
0.015
0.785
0.310
MILLIMETERS
MIN
-
0.36
0.36
1.14
0.58
0.20
0.20
-
5.59
MAX
5.08
0.66
0.58
1.65
1.14
0.46
0.38
19.94
7.87
2.54 BSC
7.62 BSC
3.81 BSC
3.18
0.38
0.13
0.13
90
o
-
-
-
-
14
5.08
1.52
-
-
105
o
0.38
0.76
0.25
0.038
NOTES
-
2
3
-
4
2
3
-
-
-
-
-
-
5
6
7
-
-
-
-
2
8
Rev. 0 4/94
E
e
A
e
e
A/2
c
0.100 BSC
0.300 BSC
0.150 BSC
0.125
0.015
0.005
0.005
90
o
-
-
-
-
14
0.200
0.060
-
-
105
o
0.015
0.030
0.010
0.0015
ccc M C A - B S D S
aaa
M C A - B S D S
NOTES:
1. Index area: A notch or a pin one identification mark shall be located
adjacent to pin one and shall be located within the shaded area
shown. The manufacturer’s identification shall not be used as a pin
one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be mea-
sured at the centroid of the finished lead surfaces, when solder dip
or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension M
applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a par-
tial lead paddle. For this configuration dimension b3 replaces di-
mension b2.
5. Dimension Q shall be measured from the seating plane to the base
plane.
6. Measure dimension S1 at all four corners.
7. Measure dimension S2 from the top of the ceramic body to the near-
est metallization or lead.
8. N is the maximum number of terminal positions.
9. Braze fillets shall be concave.
10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
11. Controlling dimension: INCH.
aaa
bbb
ccc
M
N
5
FN3025.5
July 12, 2013
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参数对比
与5962R9569002VCC相近的元器件有:HS0-5104ARH/SAMPLE、5962R9569002VXC。描述及对比如下:
型号 5962R9569002VCC HS0-5104ARH/SAMPLE 5962R9569002VXC
描述 QUAD OP-AMP, 3000uV OFFSET-MAX, 8MHz BAND WIDTH, CDIP14, ROHS COMPLIANT, HERMETIC SEALED, METAL SEALED, CERAMIC, SBDIP-14 QUAD OP-AMP, 3000uV OFFSET-MAX, 8MHz BAND WIDTH, UUC14, ROHS COMPLIANT, DIE-14 QUAD OP-AMP, 3000uV OFFSET-MAX, 8MHz BAND WIDTH, CDFP14, ROHS COMPLIANT, HERMETIC SEALED, METAL SEALED, CERAMIC, DFP-14
是否Rohs认证 符合 符合 符合
厂商名称 Renesas(瑞萨电子) Renesas(瑞萨电子) Renesas(瑞萨电子)
包装说明 DIP, DIE, DFP,
Reach Compliance Code compliant compliant compli
ECCN代码 USML XV(E) USML XV(E) USML XV(E)
放大器类型 OPERATIONAL AMPLIFIER OPERATIONAL AMPLIFIER OPERATIONAL AMPLIFIER
最大输入失调电压 3000 µV 3000 µV 3000 µV
JESD-30 代码 R-CDIP-T14 R-XUUC-N14 R-CDFP-F14
JESD-609代码 e4 e4 e4
功能数量 4 4 4
端子数量 14 14 14
最高工作温度 125 °C 125 °C 125 °C
最低工作温度 -55 °C -55 °C -55 °C
封装主体材料 CERAMIC, METAL-SEALED COFIRED UNSPECIFIED CERAMIC, METAL-SEALED COFIRED
封装代码 DIP DIE DFP
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 IN-LINE UNCASED CHIP FLATPACK
峰值回流温度(摄氏度) NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
认证状态 Not Qualified Not Qualified Not Qualified
标称压摆率 2 V/us 2 V/us 2 V/us
表面贴装 NO YES YES
技术 BIPOLAR BIPOLAR BIPOLAR
温度等级 MILITARY MILITARY MILITARY
端子面层 Gold (Au) Gold (Au) Gold (Au)
端子形式 THROUGH-HOLE NO LEAD FLAT
端子位置 DUAL UPPER DUAL
处于峰值回流温度下的最长时间 NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
总剂量 100k Rad(Si) V 100k Rad(Si) V 100k Rad(Si) V
标称均一增益带宽 8000 kHz 8000 kHz 8000 kHz
长度 19.94 mm - 9.91 mm
筛选级别 MIL-PRF-38535 Class V - MIL-PRF-38535 Class V
座面最大高度 5.08 mm - 2.92 mm
端子节距 2.54 mm - 1.27 mm
宽度 7.62 mm - 6.285 mm
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