17
QPro Virtex 2.5V Radiation-Hardened FPGAs
DS028 (v2.1) November 5, 2010
Product Specification
Features
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0.22 µm 5-layer epitaxial process
QML certified
Radiation-hardened FPGAs for space and satellite
applications
Guaranteed total ionizing dose to 100K Rad(si)
Latch-up immune to LET = 125 MeV cm
2
/mg
SEU immunity achievable with recommended
redundancy implementation
Guaranteed over the full military temperature range
(–55°C to +125°C)
Fast, high-density Field-Programmable Gate Arrays
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Densities from 100k to 1M system gates
System performance up to 200 MHz
Hot-swappable for Compact PCI
16 high-performance interface standards
Connects directly to ZBTRAM devices
Four dedicated delay-locked loops (DLLs) for
advanced clock control
Four primary low-skew global clock distribution
nets, plus 24 secondary global nets
LUTs configurable as 16-bit RAM, 32-bit RAM,
16-bit dual-ported RAM, or 16-bit Shift Register
Configurable synchronous dual-ported 4k-bit
RAMs
Fast interfaces to external high-performance RAMs
Dedicated carry logic for high-speed arithmetic
Dedicated multiplier support
Cascade chain for wide-input functions
Abundant registers/latches with clock enable, and
dual synchronous/asynchronous set and reset
Internal 3-state bussing
IEEE 1149.1 boundary-scan logic
Die-temperature sensing device
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Supported by FPGA Foundation™ and Alliance
Development Systems
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Complete support for Unified Libraries, Relationally
Placed Macros, and Design Manager
Wide selection of PC and workstation platforms
Unlimited reprogrammability
Four programming modes
SRAM-based in-system configuration
Available to Standard Microcircuit Drawings. Contact
Defense Supply Center Columbus (DSCC) for more
information at
http://www.dscc.dla.mil
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5962-99572 for XQVR300
5962-99573 for XQVR600
5962-99574 for XQVR1000
Multi-standard SelectIO™ interfaces
Description
The QPro™ Virtex® family delivers high-performance,
high-capacity programmable logic solutions. Dramatic
increases in silicon efficiency result from optimizing the new
architecture for place-and-route efficiency and exploiting an
aggressive 5-layer-metal 0.22 µm CMOS process. These
advances make QPro Virtex FPGAs powerful and flexible
alternatives to mask-programmed gate arrays. The Virtex
radiation-hardened family comprises the three members
shown in
Table 1.
Building on experience gained from previous generations of
FPGAs, the Virtex family represents a revolutionary step
forward in programmable logic design. Combining a wide
variety of programmable system features, a rich hierarchy of
fast, flexible interconnect resources, and advanced process
technology, the QPro Virtex family delivers a high-speed
and high-capacity programmable logic solution that
enhances design flexibility while reducing time-to-market.
Refer to the Virtex 2.5V FPGA commercial data sheet at
http://www.xilinx.com/support/documentation/virtex.htm
for
more information on device architecture and timing
specifications.
Built-in clock-management circuitry
Hierarchical memory system
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Flexible architecture that balances speed and density
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© Copyright 2001–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. All other trademarks are the property of their respective owners.
DS028 (v2.1) November 5, 2010
Product Specification
www.xilinx.com
1
QPro Virtex 2.5V Radiation-Hardened FPGAs
Table 1:
QPro Virtex FPGA Radiation-Hardened FPGA Family Members
Device
XQVR300
XQVR600
XQVR1000
System Gates CLB Array Logic Cells Maximum Available I/O Block RAM Bits Maximum Select RAM Bits
322,970
661,111
1,124,022
32x48
48x72
64x96
6,912
15,552
27,648
162
162
404
65,536
98,304
131,072
98,304
221,184
393,216
Radiation Specifications
Table 2:
Radiation Specifications
(1)
Symbol
TID
SEL
Description
Total Ionizing Dose
Method 1019, Dose Rate ~9.0 rad(Si)/sec
Single Event Latch-up Immunity
Heavy Ion Saturation Cross Section
LET > 125 MeV cm
2
/mg
Single Event Upset CLB Flip-flop
Heavy Ion Saturation Cross Section
Single Event Upset Configuration Latch
Heavy Ion Saturation Cross Section
Single Event Upset Configuration Latch
Proton (63 MeV) Saturation Cross Section
Single Event Upset Block RAM Bit
Heavy Ion Saturation Cross Section
Min
100
–
Max
–
0
Units
krad(Si)
(cm
2
/Device)
SEU
FH
SEU
CH
SEU
CP
SEU
BH
Notes:
1.
–
–
–
–
6.5E – 8
8.0E – 8
2.2E – 14
1.6E – 7
(cm
2
/Bit)
(cm
2
/Bit)
(cm
2
/Bit)
(cm
2
/Bit)
For more information, refer to “Radiation Test Results of the Virtex FPGA for Space Based Reconfigurable Computing” and “SEU Mitigation
Techniques for Virtex FPGAs in Space Applications” at
http://www.xilinx.com/esp/aero_def/aero_def_app.htm.
Virtex FPGA Electrical Characteristics
Based on preliminary characterization. Further changes are not expected.
All specifications are representative of worst-case supply voltage and junction temperature conditions. The parameters
included are common to popular designs and typical applications. Contact the factory for design considerations requiring
more detailed information.
DS028 (v2.1) November 5, 2010
Product Specification
www.xilinx.com
2
QPro Virtex 2.5V Radiation-Hardened FPGAs
Virtex FPGA DC Characteristics
Absolute Maximum Ratings
Table 3:
Absolute Maximum Ratings
Symbol
V
CCINT
V
CCO
V
REF
V
IN(3)
V
TS
V
CC
T
STG
T
J
Notes:
1.
Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
Power supplies can turn on in any order.
For protracted periods (e.g., longer than a day), V
IN
should not exceed V
CCO
by more that 3.6V.
Description
Supply voltage relative to GND
Supply voltage relative to GND
Input reference voltage
Input voltage relative to GND
Using V
REF
Internal threshold
Voltage applied to 3-state output
Longest supply voltage rise time from 1V to 2.375V
Storage temperature (ambient)
Junction temperature
Min/Max
–0.5 to 3.0
–0.5 to 4.0
–0.5 to 3.6
–0.5 to 3.6
–0.5 to 5.5
–0.5 to 5.5
50
–65 to +150
+150
Units
V
V
V
V
V
V
ms
C
C
2.
3.
Recommended Operating Conditions
Table 4:
Recommended Operating Conditions
Symbol
V
CCINT
V
CCO
T
IN
T
IC
Description
Supply voltage relative to GND
Supply voltage relative to GND
Input signal transition time
Initialization temperature range
(4)
Device
Min
2.5 – 5%
1.2
–
Max
2.5 + 5%
3.6
250
+125
+125
+125
+125
+125
+125
150
200
200
4.0
4.0
4.0
Units
V
V
ns
C
C
C
C
C
C
mA
mA
mA
mA
mA
mA
XQVR300
XQVR600
XQVR1000
–55
–55
–40
–55
–55
–55
–
–
–
–
–
–
T
OC
Operational temperature range
(5)
XQVR300
XQVR600
XQVR1000
ICC
INTQ
Quiescent V
CCINT
supply current
XQVR300
XQVR600
XQVR1000
ICC
CCOQ
Quiescent V
CCO
supply current
XQVR300
XQVR600
XQVR1000
Notes:
1.
2.
3.
4.
5.
Correct operation is guaranteed with a minimum V
CCINT
of 2.25V (Nominal V
CCINT
– 10%). Below the minimum value stated above, all delay
parameters increase by 3% for each 50 mV reduction in V
CCINT
below the specified range.
At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per
C.
Input and output measurement threshold is ~50% of V
CC
.
Initialization occurs from the moment of V
CC
ramp-up to the rising transition of the INIT pin.
The device is operational after the INIT pin has transitioned High.
DS028 (v2.1) November 5, 2010
Product Specification
www.xilinx.com
3
QPro Virtex 2.5V Radiation-Hardened FPGAs
QPro Virtex FPGA Pinouts
Device/Package Combinations and Maximum User I/O
Table 5:
Device/Package Combinations and Maximum User I/O
Package
CB228
CG560
(1)
Notes:
1.
Obsolete package. CG560 is no longer available. It is listed for information purposes only.
Maximum User I/O (Excluding Dedicated Clock Pins)
XQVR300
162
–
XQVR600
162
–
XQVR1000
–
404
Pinout Tables
Table 6
and
Table 7
list the locations of special-purpose and power-supply pins. Pins not listed are user I/Os.
Table 6:
Virtex FPGA Ceramic Column Grid (CG560) Pinout for the XQVR1000
Pin Name
GCK0
GCK1
GCK2
GCK3
M0
M1
M2
CCLK
PROGRAM
DONE
INIT
BUSY/DOUT
D0/DIN
D1
D2
D3
D4
D5
D6
D7
WRITE
CS
TDI
TDO
TMS
TCK
DXN
AL17
AJ17
D17
A17
AJ29
AK30
AN32
C4
AM1
AJ5
AH5
D4
E4
K3
L4
P3
W4
AB5
AC4
AJ4
D6
A2
D5
E6
B33
E29
AK29
CG560
(1)
DS028 (v2.1) November 5, 2010
Product Specification
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4
QPro Virtex 2.5V Radiation-Hardened FPGAs
Table 6:
Virtex FPGA Ceramic Column Grid (CG560) Pinout for the XQVR1000
(Cont’d)
Pin Name
DXP
V
CCINT
V
CCINT
pins are listed incrementally. Connect all
pins listed for both the required device and all
smaller devices listed in the same package.
V
CCO
, Bank 0
V
CCO
, Bank 1
V
CCO
, Bank 2
V
CCO
, Bank 3
V
CCO
, Bank 4
V
CCO
, Bank 5
V
CCO
, Bank 6
V
CCO
, Bank 7
V
REF
, Bank 0
Within each bank, if input reference voltage is not
required, all V
REF
pins are general I/O.
V
REF
, Bank 1
Within each bank, if input reference voltage is not
required, all V
REF
pins are general I/O.
V
REF
, Bank 2
Within each bank, if input reference voltage is not
required, all V
REF
pins are general I/O.
V
REF
, Bank 3
Within each bank, if input reference voltage is not
required, all V
REF
pins are general I/O.
V
REF
, Bank 4
Within each bank, if input reference voltage is not
required, all V
REF
pins are general I/O.
V
REF
, Bank 5
Within each bank, if input reference voltage is not
required, all V
REF
pins are general I/O.
V
REF
, Bank 6
Within each bank, if input reference voltage is not
required, all V
REF
pins are general I/O.
V
REF
, Bank 7
Within each bank, if input reference voltage is not
required, all V
REF
pins are general I/O.
GND
AJ28
A21, B12, B14, B18, B28, C22, C24, E9, E12, F2, H30, J1, K32, M3, N1, N29, N33,
U5, U30, Y2, Y31, AB2, AB32, AD2, AD32, AG3, AG31, AJ13, AK8, AK11, AK17,
AK20, AL14, AL22, AL27, AN25
A22, A26, A30, B19, B32
A10, A16, B13, C3, E5
B2, D1, H1, M1, R2
V1, AA2, AD1, AK1, AL2
AM2, AM15, AN4, AN8, AN12
AL31, AM21, AN18, AN24, AN30
W32, AB33, AF33, AK33, AM32
C32, D33, K33, N32, T33
A19, D20, D26, D29, E21, E23, E24, E27
CG560
(1)
A6, D7, D10, D11, D13, D16, E7, E15
B3, G5, H4, K5, L5, N5, P4, R1
V4, W5, AA4, AD3, AE5, AF1, AH4, AK2
AK13, AL7, AL9, AL10, AL16, AM4, AM14, AN3
AJ18, AJ25, AK28, AL20, AL24, AL29, AM26, AN23
V29, Y32, AA30,AD31, AE29, AK32, AE31, AH30
D31, E31, G31, H32, K31, P31, T31, L33
A1, A7, A12, A14, A18, A20, A24, A29, A32, A33, B1, B6, B9, B15, B23, B27, B31,
C2, E1, F32, G2, G33, J32, K1, L2, M33, P1, P33, R32, T1, V33, W2, Y1, Y33,
AB1, AC32, AD33, AE2, AG1, AG32, AH2, AJ33, AL32, AM3, AM7, AM11, AM19,
AM25, AM28, AM33, AN1, AN2, AN5, AN10, AN14, AN16, AN20, AN22, AN27,
AN33
C31, AC2, AK4, AL3
No Connect
Notes:
1.
Obsolete package. CG560 is no longer available. It is listed for information purposes only.
DS028 (v2.1) November 5, 2010
Product Specification
www.xilinx.com
5
