Arria V Device Overview
2013.05.06
AV-51001
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The Arria
®
V device family consists of the most comprehensive offerings of mid-range FPGAs ranging from
the lowest power for 6 gigabits per second (Gbps) and 10 Gbps applications, to the highest mid-range FPGA
bandwidth 12.5 Gbps transceivers.
The Arria V devices are ideal for power-sensitive wireless infrastructure equipment, 20G/40G bridging,
switching, and packet processing applications, high-definition video processing and image manipulation,
and intensive digital signal processing (DSP) applications.
Related Information
Arria V Device Handbook: Known Issues
Lists the planned updates to the
Arria V Device Handbook
chapters.
Key Advantages of Arria V Devices
Table 1: Key Advantages of the Arria V Device Family
Advantage
Supporting Feature
Lowest static power in its class • Built on TSMC's 28 nm process technology and includes an abundance of
hard intellectual property (IP) blocks
• Power-optimized MultiTrack routing and core architecture
• Up to 50% lower power consumption than the previous generation device
• Lowest power transceivers of any midrange family
Improved logic integration and • 8-input adaptive logic module (ALM)
differentiation capabilities
• Up to 38.38 megabits (Mb) of embedded memory
• Variable-precision digital signal processing (DSP) blocks
Increased bandwidth capacity • Serial data rates up to 12.5 Gbps
• Hard memory controllers
Hard processor system (HPS) • Tight integration of a dual-core ARM Cortex-A9 MPCore processor, hard
with integrated ARM
®
IP, and an FPGA in a single Arria V system-on-a-chip (SoC) FPGA
™
Cortex -A9 MPCore processor • Supports over 128 Gbps peak bandwidth with integrated data coherency
between the processor and the FPGA fabric
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2
Summary of Arria V Features
AV-51001
2013.05.06
Advantage
Supporting Feature
Lowest system cost
• Requires as low as four power supplies to operate
• Available in thermal composite flip chip ball-grid array (BGA) packaging
• Includes innovative features such as Configuration via Protocol (CvP),
partial reconfiguration, and design security
Summary of Arria V Features
Table 2: Summary of Features for Arria V Devices
Feature
Description
Technology
• TSMC's 28-nm process technology:
• Arria V GX, GT, SX, and ST—28-nm low power (28LP) process
• Arria V GZ—28-nm high performance (28HP) process
• Lowest static power in its class (less than 1.2 W for 500K logic elements (LEs) at 85°C
junction under typical conditions)
• 0.85 V, 1.1 V, or 1.15 V core nominal voltage
Packaging
• Thermal composite flip chip BGA packaging
• Multiple device densities with identical package footprints for seamless migration
between different device densities
• Lead, lead-free (Pb-free), and RoHS-compliant options
High-performance • Enhanced 8-input ALM with four registers
FPGA fabric
• Improved routing architecture to reduce congestion and improve compilation time
Internal memory
blocks
• M10K—10-kilobits (Kb) memory blocks with soft error correction code (ECC)
(Arria V GX, GT, SX, and ST devices only)
• M20K—20-Kb memory blocks with hard ECC (Arria V GZ devices only)
• Memory logic array block (MLAB)-640-bit distributed LUTRAM where you can use
up to 50% of the ALMs as MLAB memory
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Summary of Arria V Features
3
Feature
Description
Variable-precision
DSP
• Native support for up to four signal processing precision levels:
• Three 9 x 9, two 18 x 18, or one 27 x 27 multiplier in the
same variable-precision DSP block
• One 36 x 36 multiplier using two variable-precision DSP
blocks (Arria V GZ devices only)
• 64-bit accumulator and cascade for systolic finite impulse
responses (FIRs)
• Embedded internal coefficient memory
• Preadder/subtractor for improved efficiency
Memory controller
(Arria V GX, GT, SX,
and ST only)
Embedded Hard IP
Embedded
blocks
transceiver I/O
DDR3 and DDR2
• Custom implementation:
• Arria V GX and SX devices—up to 6.5536 Gbps
• Arria V GT and ST devices—up to 10.3125 Gbps
• Arria V GZ devices—up to 12.5 Gbps
• PCI Express
®
(PCIe
®
) Gen2 (x1, x2, or x4) and Gen1 (x1, x2,
x4, or x8) hard IP with multifunction support, endpoint, and
root port
• PCIe Gen3 (x1, x2, x4, or x8) support (Arria V GZ only)
• Gbps Ethernet (GbE) and XAUI physical coding sublayer (PCS)
• Common Public Radio Interface (CPRI) PCS
• Gigabit-capable passive optical network (GPON) PCS
• 10-Gbps Ethernet (10GbE) PCS
• Serial RapidIO
®
(SRIO) PCS
• Interlaken PCS
Clock networks
• Up to 650 MHz global clock network
• Global, quadrant, and peripheral clock networks
• Clock networks that are not used can be powered down to reduce dynamic power
Phase-locked loops • High-resolution fractional PLLs
(PLLs)
• Precision clock synthesis, clock delay compensation, and zero delay buffering (ZDB)
• Integer mode and fractional mode
• LC oscillator ATX transmitter PLLs (Arria V GZ only)
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Summary of Arria V Features
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2013.05.06
Feature
Description
FPGA
General-purpose
I/Os (GPIOs)
•
•
•
•
1.6 Gbps LVDS receiver and transmitter
800 MHz/1.6 Gbps external memory interface
On-chip termination (OCT)
3.3 V support
1
External Memory
Interface
Memory interfaces with low latency:
• Hard memory controller-up to 1.066 Gbps
• Soft memory controller-up to 1.6 Gbps
• 600 Mbps to 12.5 Gbps integrated transceiver speed
• Less than 105 mW per channel at 6 Gbps, less than 165 mW per channel at 10 Gbps,
and less than 170 mW per channel at 12.5 Gbps
• Transmit pre-emphasis and receiver equalization
• Dynamic partial reconfiguration of individual channels
• Physical medium attachment (PMA) with soft PCS that supports 9.8304 Gbps CPRI
(Arria V GT and ST only)
• PMA with hard PCS that supports up to 9.8 Gbps CPRI (Arria V GZ only)
• Hard PCS that supports 10GBASE-R and 10GBASE-KR (Arria V GZ only)
Low-power
high-speed serial
interface
• Dual-core ARM Cortex-A9 MPCore processor-up to 800 MHz maximum frequency
with support for symmetric and asymmetric multiprocessing
(Arria V SX and ST
• Interface peripherals—10/100/1000 Ethernet media access control (EMAC), USB 2.0
devices only)
On-The-GO (OTG) controller, quad serial peripheral interface (QSPI) flash controller,
NAND flash controller, Secure Digital/MultiMediaCard (SD/MMC) controller, UART,
serial peripheral interface (SPI), I2C interface, and up to 85 HPS GPIO interfaces
• System peripherals—general-purpose timers, watchdog timers, direct memory access
(DMA) controller, FPGA configuration manager, and clock and reset managers
• On-chip RAM and boot ROM
• HPS–FPGA bridges—include the FPGA-to-HPS, HPS-to-FPGA, and lightweight
HPS-to-FPGA bridges that allow the FPGA fabric to issue transactions to slaves in
the HPS, and vice versa
• FPGA-to-HPS SDRAM controller subsystem—provides a configurable interface to
the multiport front end (MPFE) of the HPS SDRAM controller
• ARM CoreSight
™
JTAG debug access port, trace port, and on-chip trace storage
Configuration
• Tamper protection-comprehensive design protection to protect your valuable IP
investments
• Enhanced advanced encryption standard (AES) design security features
• CvP
• Partial and dynamic reconfiguration of the FPGA
• Active serial (AS) x1 and x4, passive serial (PS), JTAG, and fast passive parallel (FPP)
x8, x16, and x32 (Arria V GZ) configuration options
• Remote system upgrade
HPS
1
Arria V GZ devices support 3.3 V with a 3.0 V V
CCIO
.
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Arria V Device Variants and Packages
5
Arria V Device Variants and Packages
Table 3: Device Variants for the Arria V Device Family
Variant
Description
Arria V GX
Arria V GT
Arria V GZ
FPGA with integrated 6.5536 Gbps transceivers that provides bandwidth, cost, and power
levels that are optimized for high-volume data and signal-processing applications
FPGA with integrated 10.3125 Gbps transceivers that provides enhanced high-speed
serial I/O bandwidth for cost-sensitive data and signal processing applications
FPGA with integrated 12.5 Gbps transceivers that provides enhanced high-speed serial
I/O bandwidth for high-performance and cost-sensitive data and signal processing
applications
SoC FPGA with integrated ARM-based HPS and 6.5536 Gbps transceivers
SoC FPGA with integrated ARM-based HPS and 10.3125 Gbps transceivers
Arria V SX
Arria V ST
Arria V GX
This section provides the available options, maximum resource counts, and package plan for the Arria V GX
devices.
Available Options
Figure 1: Sample Ordering Code and Available Options for Arria V GX Devices—Preliminary
Embedded Hard IPs
B : No hard PCIe or hard
memory controller
M : 1 hard PCIe and 2 hard
memory controllers
F : Maximum 2 hard PCIe and
4 hard memory controllers
Transceiver Count
D : 9
G : 18
H : 24
K : 36
Package Type
F : FineLine BGA (FBGA)
Operating Temperature
C : Commercial (T
J
= 0° C to 85° C)
I : Industrial (T
J
= -40° C to 100° C)
Family Signature
5A : Arria V
5A
GX
F
B5
H
4
F
35
I
3
N
Optional Suffix
Indicates specific device
options or shipment method
N : Lead-free packaging
ES : Engineering sample
FPGA Fabric
Speed Grade
3 (fastest)
4
5
6
Family Variant
GX : 6-Gbps transceivers
Member Code
A1: 75K logic elements
A3: 156K logic elements
A5: 190K logic elements
A7: 242K logic elements
B1: 300K logic elements
B3: 362K logic elements
B5: 420K logic elements
B7: 504K logic elements
Transceiver
Speed Grade
4 : 6.5536 Gbps
6 : 3.1250 Gbps
Package Code
27 : 672 pins
31 : 896 pins
35 : 1,152 pins
40 : 1,517 pins
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