VersaClock
®
Programmable Clock Generator
5P35021
DATASHEET
Description
The 5P35021 is the latest VersaClock programmable clock
generator and is designed for low-power, consumer, and
high-performance PCI Express applications. The 5P35021
device is a 3 PLLs architecture design; each PLL is
individually programmable and allows up to 3 unique
frequency outputs.
The 5P35021 has built-in unique features such as Proactive
Power Saving (PPS), Performance-Power Balancing (PPB),
Overshot Reduction Technology (ORT) and extreme low
power DCO. An internal OTP memory allows the user to store
the configuration in the device. After power up, the user can
change the device register settings through the I
2
C interface
when I
2
C mode is selected. It also has programmable VCO
and PLL source selection to allow the user to do
power-performance optimization based on the application
requirements.
The device provides one single-ended output and two pairs of
differential outputs that support LVCMOS, LVPECL, LVDS and
LPHCSL. The low power 32.768kHz clock is supported with
only less than 2µA current consumption for system RTC
reference clock.
Features
•
Configurable OE pin function as OE, PD#, PPS or DFC
•
•
•
•
•
•
•
control function
Configurable PLL bandwidth/minimizes jitter peaking
PPS: Proactive Power Saving features save power during
the end device power down mode
PPB: Performance- Power Balancing feature allow user to
minimum power consumption base on required
performance
DFC: Dynamic Frequency Control feature allows user to
program up to 4 difference frequencies and switch
dynamically
Spread spectrum clock support to lower system EMI
Store user configuration into OTP memory
I
2
C interface
Key Specifications
•
PCIe clocks phase jitter: PCIe Gen3
•
Differential clocks < 3 ps rms jitter integer range 12kHz–
•
20MHz
< 2 µA DCO to generate 32.768kHz clock
Output Features
•
2 DIFF outputs with configurable LPHSCL, LVDS, LVPECL,
•
•
•
LVCMOS output pairs. 1MHz–500MHz (160MHz/ with
LVCMOS mode)
1 LVCMOS output: 1MHz–160MHz
Maximum 5 LVCMOS outputs as 1 × SE + 2 × DIFF_T/C as
LVCMOS
Low Power 32.768kHz clock supported on SE1
Typical Applications
•
PCIe Gen1/2/3 clock generator
•
Consumer application crystal replacements
•
SmartDevice, Handheld, Computing and Consumer
applications
Pin Assignment
VDDDIFF2
VSSDIFF2
VSSDIFF1
16
15
14
DIFF2B
18
DIFF2
20
19
17
VDDA
SDA_DFCO
SEL_DFC/SCL_DFC1
CLKIN/X2
CLKINB/X1
1
2
3
4
5
6
7
8
9
10
DIFF1
DIFF1B
VDDDIFF1
OE1
SE1
5P35021
13
12
11
VBAT
5P35021 NOVEMBER 30, 2017
1
VDDSE1
VSS
VSSSE1
VDD33
©2017 Integrated Device Technology, Inc.
5P35021 DATASHEET
Functional Block Diagram
DIV1/REF
OSC
MUX
DIV 1
DIV3
MUX
CLKINB/X1
CLKIN/X2
PLL1
DIV 2
DIV1/REF
DIV3
MUX
VDDDIFF2
DIFF2
DIFF2B
VDDDIFF1
DIFF1
DIFF1B
VBAT
VDD33
Power
Monitor
POR
MUX
PLL2
MUX
DIV 3
MUX
DIV 4
VDDA
MUX
PLL3
DIV 5
VSS
Calibration
DIV4/REF
DIV5
32K
MUX
OE1
SE1
VDDSE1
32.768K
DCO
SCL_DFC1
SDA_DFC0
I2C Engine
Overshoot Reduction
(ORT)
Dynamic Frequency Control Logic (DFC)
OTP memory (1 configuration )
Proactive Power Saving Logic (PPS)
Timer
Power Group
Power supply table
VDDSE1
VDDDIFF1
VDDDIFF2
VDD33
VBAT
VDDA
SE
SE1
DIFF1
DIFF2
DIV3/4
DIV1
DIV5
DIV2
MUXPLL2
MUXPLL1
PLL2
PLL3
PLL1
DCO
DCO
REF
Xtal
Xtal
DIFF
DIV
MUX
PLL
DCO
REF
Xtal
* VDDSEx for non-32kHz outputs should be OFF when VDDA/VDD3 turn OFF, VBAT mode only support
32.768kHz outputs from SE1-3.
* VBAT power ramp up should be same or earlier than other VDD power rail.
Output Source Table
Source:
Xtal REF
32.768kHz
PLL1
PLL2
PLL3
Outputs:
SE1
Xtal REF
32.768kHz
PLL2
PLL3
DIFF1
Xtal REF
PLL1
PLL2
PLL3
DIFF2
Xtal REF
PLL1
PLL2
PLL3
VERSACLOCK
®
PROGRAMMABLE CLOCK GENERATOR
2
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5P35021 DATASHEET
Output Source Selection Register Setting Table
SE1
From 32K
From PLL3 + Divider 5
From PLL2 + Divider 4
From REF + Divider 4
B36<4>
0
1
1
1
B36<3>
1
0
1
1
B31<1>
0
0
1
0
B29<3>
0
0
0
1
DIFF1
From PLL1 + Divider 1
From PLL2 + Divider 3
From REF + Divider 1
DIFF2
From PLL1 + Divider 1
From PLL2 + Divider 3
From REF + Divider 1
B34<7>
0
1
0
B35<7>
0
1
0
B0<3>
0
0
1
B0<3>
0
0
1
Glossary of Features
Term
DFC
Function Description
Dynamic Frequency Control, from selected PLL to support four VCO frequencies,
means two different output frequencies by assign H/W pin state changes.
Overshoot Reduction, when the DFC dynamic frequency change is functional, the
VCO change frequency smoothly to target frequency without overshoot or under
shoot.
Output Enable function, each output can be controlled by assigned OE pin, the
dedicated OE pin can be OTP programmable as Global Power Down function (PD#)
or Output enable (OE) or proactive power saving function (PPS) or RESET pin
function.
Spread spectrum clock.
LVCMOS outputs with slew rate control - slow and fast.
Proactive Power Saving, utilize OE pin as monitor pin for end device X2 clock status,
details see PPS function .description
Apply to
PLL2
ORT
PLL2
OE
SS
Slew Rate
PPS
OE1
PLL1/PLL2
LVCMOS
SE1
NOVEMBER 30, 2017
3
VERSACLOCK
®
PROGRAMMABLE CLOCK GENERATOR
5P35021 DATASHEET
Pin Descriptions
Number
1
2
Name
VDDA
SDA_DFC0
Type
Power
I/O
Description
VDD 3.3V.
I2C DATA pin, can be setup become DFC0 by OTP programming.
I2C CLK pin,
SEL_DFC is a latch input pin during the power up
High on power on: I2C mode as SCLK function,
Low on power on: SCL and SDA as DFC function pins.
Crystal oscillator interface output or differential clock input pin (CLKIN).
Crystal oscillator interface input or differential clock input pin (CLKINB).
Power supply pin for 32.768kHz DCO, usually connect to coin cell battery, 2.5-3.3V.
Connect to ground.
VDD 3.3V.
Connect to ground.
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for SE1.
Output Clock SE1.
OE1’s function selected from OTP preprogram register bits.
OE1 pull-up to 6.5V when burn OTP registers.
Refer to OE function table for details.
Output power supply. Connect to 2.5 to 3.3V. Sets output voltage levels for DIFF1.
Differential clock output 1_Complement, can be OTP pre-program to
LVCMOS/LPHCSL/LVDS/LVPECL output type.
Differential clock output 1_True, can be OTP pre-program to
LVCMOS/LPHCSL/LVDS/LVPECL output type.
Connect to ground.
Output power supply. Connect to 2.5 to 3.3V. Sets output voltage levels for DIFF2.
Differential clock output 2_Complement, can be OTP pre-program to
LVCMOS/LPHCSL/LVDS/LVPECL output type.
Differential clock output 2_True, can be OTP pre-program to
LVCMOS/LPHCSL/LVDS/LVPECL output type.
Connect to ground.
Connect to ground.
3
SEL_DFC/SCL_DFC1
Input
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
CLKIN/X2
CLKINB/X1
VBAT
VSS
VDD33
VSSSE1
VDDSE1
SE1
OE1
VDDDIFF1
DIFF1B
DIFF1
VSSDIFF1
VDDDIFF2
DIFF2B
DIFF2
VSSDIFF2
EPAD
I/O
Input
Power
Power
Power
Power
Power
Output
Input
Power
Output
Output
Power
Power
Output
Output
Power
Power
VERSACLOCK
®
PROGRAMMABLE CLOCK GENERATOR
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5P35021 DATASHEET
Device Feature and Function
DFC–Dynamic Frequency Control
•
OTP program (Only) setup 4 different feedback fractional divider (4 VCO frequencies) that apply to PLL2
•
ORT (overshoot reduction) function will be applied automatically during the VCO frequency change
•
Smooth frequency incremental or decremental from current VCO to targeted VCO base on DFC hardware pins selection
DFC Block Diagram
M divider
PLL2
OUT DIV
Selector
00
01
10
11
DFC1:0
N divider
N divider
N divider
N divider
OTP/I2C
DFC Function Priority Table
DFC_EN
bit(W32[4])
0
1
1
1
1
1
OE1_fun_sel
(W30[6:5])
x
11 (DFC)
11 (DFC)
00-10
00-10
00-10
*OE3_fun_sel
(W30[3:2])
x
00-10 (DFC)
11 (DFC)
11
00-10
00-10
SCL_DFC1
x
x
x
x
0
1
DFC[1:0]
0
[0,OE1]
[OE3,OE1]
Not permit
[SCL_DFC1,
SDA_DFC0]
W30[1:0]
Notes
DFC disable
One pin DFC -
OE1
Two pin DFC -
OE3,OE1
Not supported
I2C pin as DFC
control pins mode
I2C control DFC
mode
* 5P35021 has only OE1 pin for DFC function hardware pin selection. For OE1/OE3 two pins DFC control, use 5P35023 24-
QFN package device.
DFC Function Programming
•
Register B63b3:2 select DFC00–DFC11 configuration.
•
Byte16–19 are the register for PLL2 VCO setting, base on B63b3:2 configuration selection, the data write to B16–19 will be
•
•
store in selected configuration OTP memory.
Refer to DFC function priority table, select proper control pin(s) to activate DFC function.
Note the DFC function can also be controlled by I
2
C access.
5
VERSACLOCK
®
PROGRAMMABLE CLOCK GENERATOR
NOVEMBER 30, 2017
