VersaClock
®
Programmable Clock
Generator
Datasheet
5P35023
Description
The 5P35023 is a VersaClock programmable clock generator and
is designed for low-power, consumer, and high-performance PCI
Express applications. The 5P35023 device is a three PLL
architecture design, and each PLL is individually programmable
and allowing for up to six unique frequency outputs.
The 5P35023 has built-in unique features such as Proactive
Power Saving (PPS), Performance-Power Balancing (PPB),
Overshot Reduction Technology (ORT) and Extreme Low Power
DCO. An internal OTP memory allows the user to store the
configuration in the device. After power up, the user can change
the device register settings through the I2C interface when I2C
mode is selected.
The device has programmable VCO and PLL source selection to
allow the user to do power-performance optimization based on the
application requirements. It also supports three single-ended
outputs and two pair of differential outputs that support LVCMOS,
LVPECL, LVDS and LP-HCSL. A Low Power 32.768kHz clock is
supported with only less than 2µA current consumption for system
RTC reference clock.
Features
▪
Configurable OE pin function as OE, PD#, PPS or DFC control
function
▪
Configurable PLL bandwidth; minimizes jitter peaking
▪
PPS: Proactive Power Saving features save power during the
end device power down mode
▪
PPB: Performance Power Balancing feature allows minimum
power consumption based on required performance
▪
DFC: Dynamic Frequency Control feature allows user to
dynamically switch between and up to 4 different frequencies
smoothly
▪
Two PLLs support independent spread spectrum clocks to
lower system EMI
▪
Store user configuration into OTP memory
▪
I
2
C interface
▪
Available in Automotive Grade 2 (-40°C to +105°C) or
industrial (-40° to +85°) temperature ranges
Output Features
▪
2 DIFF outputs with configurable LP-HSCL, LVDS, LVPECL,
LVCMOS output pairs. 1MHz–500MHz (160MHz with LVCMOS
mode)
▪
3 LVCMOS outputs: 1MHz–160MHz
Typical Applications
▪
▪
▪
▪
▪
PCIe Gen1–3 clock generator
Consumer application crystal replacements
SmartDevice, Handheld
Computing and consumer applications
Automotive applications (infotainment, dashboard,
camera/vision, computing, networking)
▪
Maximum 8 LVCMOS outputs as REF + 3 × SE + 2 × DIFF_T/C
as LVCMOS
▪
Low power 32.768kHz clock supported for all SE1–SE3
Key Specifications
▪
PCIe clocks phase jitter: PCIe Gen3
▪
Differential clocks < 1.5ps rms jitter integer range 12kHz–
20MHz
©2019 Integrated Device Technology, Inc.
1
May 15, 2019
5P35023 Datasheet
Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Key Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Output Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Power Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Output Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Device Features and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
DFC – Dynamic Frequency Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
DFC Function Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PPS – Proactive Power Saving Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
PPS Function Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Timer Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
OE Pin Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Reference Input and Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Crystal Input (X1/X2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Analog Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Digital Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
ORT–VCO Overshoot Reduction Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PLL Features and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output Clock Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
PCI Express Jitter Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Spread Spectrum Generation Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
I2C Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
I2C Mode Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Glossary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Marking Diagrams (industrial) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Marking Diagrams (automotive) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
©2019 Integrated Device Technology, Inc.
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5P35023 Datasheet
Block Diagram
DIV1/REF
OSC
MUX
DIV1
DIV3
MUX
CLKINB/X1
CLKIN/X2
PLL1
DIV2
DIV1/REF
DIV3
MUX
VDDDIFF2
DIFF2
DIFF2B
VDDDIFF1
DIFF1
DIFF1B
OE3
SE3
VDDSE3
OE2
SE2
VDDSE2
OE1
SE1
VDDSE1
REF
DIV2
VBAT
VDD33
Power
Monitor
POR
MUX
PLL2
MUX
DIV3
DIV4/REF
32K
MUX
MUX
DIV4
DIV4/REF
DIV5
MUX
VDDA
MUX
32K
PLL3
DIV5
VSS
Calibration
DIV4/REF
DIV5
32K
MUX
32.768K
DCO
SCL_DFC1
SDA_DFC0
I2C Engine
Overshoot Reduction
(ORT)
Dynamic Frequency Control Logic (DFC)
OTP memory (1 configuration)
Proactive Power Saving Logic (PPS)
Timer
Pin Assignments
Figure 1. Pin Assignments for 4 x 4 mm 24-VFQFPN Package – Top View
VDDDIFF2
VDDSE3
20
DIFF2B
DIFF2
OE3
24
23
22
21
SE3
19
18
17
16
VDDA
SDA_DFCO
SEL_DFC/SCL_DFC1
CLKIN/X2
CLKINB/X1
VBAT
1
2
3
4
5
6
7
8
9
10
11
12
DIFF1
DIFF1B
VDDDIFF1
OE1
SE1
VDDSE1
5P35023
15
14
13
VDDSE2
VDD33
REF
24-VFQFPN
©2019 Integrated Device Technology, Inc.
3
OE2
SE2
NC
May 15, 2019
5P35023 Datasheet
Pin Descriptions
Table 1. Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Name
V
DDA
SDA_DFC0
SEL_DFC/
SCL_DFC1
CLKIN/X2
CLKINB/X1
V
BAT
NC
REF
V
DD33
OE2
V
DDSE2
SE2
V
DDSE1
SE1
OE1
V
DDDIFF1
DIFF1B
DIFF1
SE3
V
DDSE3
OE3
V
DDDIFF2
DIFF2B
DIFF2
EPAD
Type
Power
I/O
Input
I/O
Input
Power
—
Output
Power
Input
Power
Output
Power
Output
Input
Power
Output
Output
Output
Power
Input
Power
Output
Output
Power
V
DD
3.3V
Description
I
2
C data pin. The pin can be DFC0 function by pin 3 SEL_DFC power-on latch status.
I
2
C CLK pin.
SEL_DFC is a latch input pin during the power-up.
High on power-on: I
2
C mode as SCLK function.
Low on power-on: SCL and SDA as DFC function control pins.
Crystal oscillator interface output or differential clock input pin (CLKIN).
Crystal oscillator interface input or differential clock input pin (CLKINB) or single-ended
clock input.
Power supply pin for 32.768kHz DCO; usually connect to coin cell battery, 3.0V–3.3V.
No connect.
3.3V reference clock output.
V
DD
3.3V.
Output enable control 2, multi-function pin. Refer to
OE Pin Functions
table.
Output power supply. Connect to 1.8 –3.3V. Sets output voltage levels for SE2.
Output clock SE2.
Output power supply. Connect to 1.8V–3.3V. Sets output voltage levels for SE1.
Output clock SE1.
OE1’s function selected from OTP pre-programmed register bits.
OE1 pull to 6.5V when burn OTP registers.
Refer to
OE Pin Functions
table for details.
Output power supply. Connect to 2.5V–3.3V. Sets output voltage levels for DIFF1.
Differential clock output 1_Complement; can be OTP pre-programmed to
LVCMOS/LPHCSL/LVDS/LVPECL output type.
Differential clock output 1_True; can be OTP pre-programmed to
LVCMOS/LP-HCSL/LVDS/LVPECL output type.
Output clock SE3.
Output power supply. Connect to 1.8V–3.3V. Sets output voltage levels for SE3.
Output enable control 3, multi-function pin. Refer to
OE Pin Functions
table.
Output power supply. Connect to 2.5V–3.3V. Sets output voltage levels for DIFF2.
Differential clock output 2_Complement; can be OTP pre-programmed to
LVCMOS/LP-HCSL/LVDS/LVPECL output type.
Differential clock output 2_True; can be OTP pre-programmed to
LVCMOS/LP-HCSL/LVDS/LVPECL output type.
Connect to ground pad.
©2019 Integrated Device Technology, Inc.
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May 15, 2019
5P35023 Datasheet
Power Group
Table 2. Power Group
Power Supply
V
DDSE1
V
DDSE2
V
DDSE3
V
DDDIFF1
V
DDDIFF2
V
DD33
V
BAT 1
V
DDA
1
2
SE
SE1
2
SE2
2
SE3
2
DIFF
DIV
MUX
PLL
DCO
REF
Xtal
DIFF1
DIFF2
DIV3/4
DIV1
DIV5
DIV2
MUXPLL2
MUXPLL1
PLL2
PLL3
PLL1
DCO
DCO
REF
Xtal
Xtal
V
BAT
power ramp-up must be the same or earlier time or as other V
DD
s.
V
DDSEx
for non-32kHz outputs should be OFF when V
DDA
/V
DD33
turns OFF; V
BAT
mode only supports 32.768kHz outputs from SE1–3.
Output Sources
Table 3. Output Source
Outputs
Source
Xtal REF
32.768kHz
PLL1
PLL2
PLL3
PLL2
PLL3
PLL2
PLL3
REF
Xtal REF
SE1
Xtal REF
32.768kHz
SE2
Xtal REF
32.768kHz
SE3
Xtal REF
32.768kHz
PLL1
PLL2
PLL1
PLL2
PLL3
PLL1
PLL2
PLL3
DIFF1
DIFF2
Table 4. Output Source Selection Register Settings
SE1
From 32kHz
From PLL3 + Divider 5
From PLL2 + Divider 4
From REF + Divider 4
B36<4>
0
1
1
1
B36<3>
1
0
1
1
B31<1>
0
0
1
0
B29<3>
0
0
0
1
©2019 Integrated Device Technology, Inc.
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May 15, 2019
