DATASHEET
1.8 VOLT DDR2/800 ZERO DELAY BUFFER
Description
The IDT5P61006 is a low-cost, low voltage zero delay
buffer for DDR2/800 applications. Using analog/digital
Phase-Locked Loop techniques, the device accepts a 425
MHz clock input and provides a zero-delay output of the
same frequency.
The IDT5P61006 features an on-chip feedback circuit,
eliminating the need for external feedback traces and
components.
IDT5P61006
Features
•
•
•
•
•
•
•
Packaged in 8-pin TSSOP
For DDR2/800 applications
Maximum input clock frequency of 425 MHz
Output duty cycle of 45/55
Operating voltage of 1.8 V
Industrial temperature range of -40 to +85° C
Advanced, low-power CMOS process
Block Diagram
1.8V VDD
INP
INN
PLL
OUTN
OUTP
Internal Feedback
GND
IDT®
1.8 VOLT DDR2/800 ZERO DELAY BUFFER
1
IDT5P61006
REV C 082211
IDT5P61006
1.8 VOLT DDR2/800 ZERO DELAY BUFFER
DIFFERENTIAL ZDB
Pin Assignment
VSS
INP
INN
VSS
1
2
3
4
8
7
6
5
VDD
OUTP
OUTN
VDD
8-Pin Package
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
VSS
INP
INN
VSS
VDD
OUTN
OUTP
VDD
Pin
Type
GND
Input
Input
GND
Power
Output
Output
Power
Pin Description
Connect this pin to ground.
Clock input with a (10k-100k Ohm) internal pull-down resistor.
Complementary clock input with a (10k-100k Ohm) internal pull-down
resistor.
Connect this pin to ground.
Connect this pin to 1.8 V.
Complementary Clock output. PLL power down and output will be LOW
when there is no clock input signal or both INP & INN pins are LOW.
Clock output. PLL power down and output will be LOW when there is no
clock input signal or both INP & INN pins are LOW.
Connect this pin to 1.8 V.
IDT®
1.8 VOLT DDR2/800 ZERO DELAY BUFFER
2
IDT5P61006
REV C 082211
IDT5P61006
1.8 VOLT DDR2/800 ZERO DELAY BUFFER
DIFFERENTIAL ZDB
External Components
The IDT5P61006 requires a minimum number of external
components for proper operation.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) The 4.7 µF, 0.1 µF and 2200 pF decoupling capacitors
should be mounted on the component side of the board as
close to the VDD pin as possible. No vias should be used
between decoupling capacitor and VDD pin. The PCB trace
to VDD pin should be kept as short as possible, as should
the PCB trace to the ground via.
2) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers. Other signal traces should be routed away from the
IDT5P61006. This includes signal traces just underneath
the device, or on layers adjacent to the ground plane layer
used by the device.
Decoupling Capacitor
Decoupling capacitors of 4.7 µF, 0.1 µF and 2200 pF must
be connected between VDD (pins 5, 8) and GND (pins 1, 4),
as close to these pins as possible. For optimum device
performance, the decoupling capacitor should be mounted
on the component side of the PCB. Avoid the use of vias in
the decoupling circuit.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the IDT5P61006. These ratings, which
are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at
these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Storage Temperature
Junction Temperature
Soldering Temperature
2.5 V
Rating
-0.5 V to VDD+0.5 V
-65 to +150° C
125° C
260° C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured with respect to GND)
Min.
-40
+1.7
Typ.
+1.8
Max.
+85
+1.9
Units
°
C
V
IDT®
1.8 VOLT DDR2/800 ZERO DELAY BUFFER
3
IDT5P61006
REV C 082211
IDT5P61006
1.8 VOLT DDR2/800 ZERO DELAY BUFFER
DIFFERENTIAL ZDB
Electrical Characteristics - Input/Supply/Common Output Parameters
(note1)
Unless stated otherwise,
VDD = 1.8 V ±0.1 V,
Ambient Temperature -40 to +85° C
Parameter
Supply Voltage
Supply Current
Low-level input voltage
High level input voltage
DC input signal voltage
(note 2)
Differential input signal
voltage (note 3)
Input differential cross
voltage (note4)
Output differential signal
voltage
Output differential cross
voltage (note4)
Output High Voltage
Low-level Output Voltage
Input Capacitance
5
Output Capacitance
5
Notes:
Symbol
V
DD
I
DD
V
IL
V
IH
V
IN
V
ID
V
IX
V
OD
V
OX
V
OH
V
OL
C
IN
C
OUT
Conditions
no load, 333 MHz
no load, 400 MHz
INP, INN
INP, INN
Min.
1.7
Typ.
1.8
65
73
Max.
1.9
75
85
0.35V
DD
Units
V
mA
mA
V
V
V
V
V
V
0.65 xV
DD
-0.3
0
V
DD
+0.3
V
DD
+ 0.4
DC - INP, INN
0.3
V
DD
/2 - 0.15 V
DD
/2 V
DD
/2 + 0.15
DC - OUTP, OUTN
0.6
V
DD
/2 - 0.10
I
OH
= -100 mA
I
OH
= -9 mA
I
OH
= 100 mA
I
OH
= 9 mA
V
I
= GND or V
DD
V
OUT
= GND or V
DD
2
2
V
DD
- 0.2
1.1
1.45
0.25
0.1
0.6
3
3
V
DD
/2 + 0.10
V
V
V
V
pF
pF
1. Unused inputs must be held high or low to prevent them from floating.
2. DC input signal voltage specifies the allowable DC execution of differential input.
3. Differential input signal voltage specifies the differential voltage [VTR-VCP] required for switching, where VTR is
the true input level and VCP is the complementary input level.
4. Differential cross-point voltage is expected to track variations of V
DD
and is the voltage at which the differential
signal must be crossing.
5. Guaranteed by design, not 100% tested in production.
IDT®
1.8 VOLT DDR2/800 ZERO DELAY BUFFER
4
IDT5P61006
REV C 082211
IDT5P61006
1.8 VOLT DDR2/800 ZERO DELAY BUFFER
DIFFERENTIAL ZDB
Timing Requirements
Unless stated otherwise,VDD
= 1.8 V ±0.1V,
Ambient Temperature -40 to +85° C
Parameter
Max clock frequency
Application frequency range
Input clock duty cycle
CLK stabilization
Symbol
freq
OP
freq
APP
d
tin
T
STAB
Conditions
Device Operation
Driving to DDR2 Memory
Note 1
Min.
125
160
30
Typ.
Max.
425
400
70
6
Units
MHz
MHz
%
uS
Note 1: Output clock stabilization time from the power-down mode after the clock transition at INP/INN.
Switching Characteristics
(note 1)
Unless stated otherwise,
VDD = 1.8 V ±0.1 V,
Ambient Temperature -40 to +85° C
Parameter
Period Jitter
Half-period Jitter
Input Slew Rate
Output Clock Slew Rate
Cycle-Cycle Period Jitter
Static Phase Offset
PLL Loop Bandwidth (-3dB
from unity gain)
Notes:
Symbol
t
jit(per)
t
jit(hper)
S
Lr1(i)
S
Lr1(o)
t
jitt(cc+)
t
jit(cc-)
t
SPO2
Conditions
160 MHz to 270 MHz
271 MHz to 400 MHz
Input Clock
Min.
-40
-75
-50
1
1.5
0
0
Typ.
Max.
40
75
50
Units
ps
ps
ps
V/ns
V/ns
ps
ps
ps
MHz
2.5
2.5
4
3
40
-40
-60
Input to Output
-160
2.0
1. Switching characteristics guaranteed for application frequency range.
2. Static phase offset between input and output shifted by device.
IDT®
1.8 VOLT DDR2/800 ZERO DELAY BUFFER
5
IDT5P61006
REV C 082211
