5SGXEA7K2F40C2ESAA,5SGXEA7K2F40C2ESAA pdf中文资料,5SGXEA7K2F40C2ESAA引脚图,5SGXEA7K2F40C2ESAA电路-Datasheet-电子工程世界

器件参数

参数名称

属性值

欧盟限制某些有害物质的使用

Not Compliant

ECCN (US)

3A001.a.7.a

Part Status

Unconfirmed

SVHC

Yes

SVHC Exceeds Threshold

Yes

Family Name

Stratix® V GX

Process Technology

28nm

User I/Os

696

Number of Registers

939000

Operating Supply Voltage (V)

0.85

Shift Registers

Utilize Memory

Logic Elements

622000

Number of Multipliers

512 (18x18)

Program Memory Type

SRAM

Embedded Memory (Kbit)

51200

Total Number of Block RAM

2560

EMACs

IP Core

Provider Name

Altera/Barco Silex/Mobiveil, Inc/Commsonic

Device Logic Units

622000

Number of Global Clocks

Device Number of DLLs/PLLs

Transceiver Channels

Transceiver Speed (Gbps)

14.1

Dedicated DSP

256

PCIe

Programmability

Yes

Reprogrammability Support

Yes

Copy Protection

In-System Programmability

Yes

Speed Grade

Differential I/O Standards

HCSL|LVDS|LVPECL

Single-Ended I/O Standards

LVCMOS|LVTTL

External Memory Interface

QDRII+SRAM|RLDRAM III|RLDRAM II|DDR3 SDRAM|DDR2 SDRAM

Minimum Operating Supply Voltage (V)

0.82

Maximum Operating Supply Voltage (V)

0.88

I/O Voltage (V)

3|2.5|1.8|1.5|1.35|1.25|1.2

Minimum Operating Temperature (°C)

Maximum Operating Temperature (°C)

Supplier Temperature Grade

Commercial

Supplier Package

FC-FBGA

Pin Count

1517

Standard Package Name

BGA

Mounting

Surface Mount

Package Height

2.7

Package Length

Package Width

PCB changed

1517

Lead Shape

Ball

参考设计

S56X、VPX FPGA 板基于 Rugged Intel Stratix V GX/GS 6U VPX 板和两个 VITA-57 FMC I/O 站点

S56X、VPX FPGA 板是一款坚固耐用的 6U VPX 卡，基于高带宽、高能效的 Intel Stratix V GX/GS FPGA。 Stratix V 专为高端应用而设计，为 I/O、路由和处理提供高水平的系统集成和灵活性。 ARM Cortex-A8 控制处理器提供完整的控制平面接口和可配置的 48 端口多千兆位收发器接口，支持多种协议，包括串行 RapidIO、PCI Expres...
[查看详情]
S5PE-DS，基于双 Intel Stratix V GX/GS PCIe 板的 PCIe FPGA 加速器板，带有 Quad QSFP+、DDR3、QDRII+ 和 RLDRAM3

S5PE-DS PCIe FPGA 加速器板是一款 PCIe x16 卡，具有两个高带宽、高能效的 Altera Stratix V GX 或 GS FPGA。 Stratix V 专为高端应用而设计，为 I/O、路由和处理提供高水平的系统集成和灵活性。 S5PE-DS 提供高达 64 GB 的 DDR3 SDRAM 以及 RLDRAM3 和 QDRII+ 选项。四个前面板 QSFP 笼提供了...
[查看详情]
S5PEF-0U-GXEA31C1-0000-10S-B10-6, S5PE-F PCIe FPGA Board 基于 Intel Stratix V GX/GS PCIe Board with VITA 57 FMC Site

S5PE-F PCIe FPGA 板是一款基于高带宽、高能效 Intel Stratix V GX/GS FPGA 的 PCIe x8 卡。 Stratix V 专为高端应用而设计，为 I/O、路由和处理提供高水平的系统集成和灵活性。 S5PE-F 是一种灵活高效的解决方案，适用于高性能网络和信号处理、信号处理和数据采集。该主板提供高达 16 GB 的 DDR3 SDRAM，具有可选的纠错码 (E...
[查看详情]
S5PH-Q，基于 Intel Stratix V GX/GS 半长 PCIe 板的 PCIe FPGA 板，具有双 QSFP+/SFP+、DDR3 和 QDRII+

S5PH-Q PCIe FPGA 板是一款基于高带宽、高能效 Altera Stratix V GX 或 GS FPGA 的半长 PCIe x8 卡。 Stratix V 专为高端应用而设计，为 I/O、路由和处理提供高水平的系统集成和灵活性。超过 16 GB 板载内存包括 DDR3 和 QDRII/II+。两个前面板 QSFP+ 笼允许两个 40GigE 接口（或八个 10GigE）直接连接...
[查看详情]

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2015.10.01

Stratix V Device Overview

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SV51001

Altera’s 28-nm Stratix

V FPGAs include innovations such as an enhanced core architecture, integrated

transceivers up to 28.05 gigabits per second (Gbps), and a unique array of integrated hard intellectual

property (IP) blocks.

With these innovations, Stratix V FPGAs deliver a new class of application-targeted devices optimized for:

• Bandwidth-centric applications and protocols, including PCI Express

(PCIe

) Gen3

• Data-intensive applications for 40G/100G and beyond

• High-performance, high-precision digital signal processing (DSP) applications

Stratix V devices are available in four variants (GT, GX, GS, and E), each targeted for a different set of

applications. For higher volume production, you can prototype with Stratix V FPGAs and use the low-

risk, low-cost path to HardCopy

V ASICs.

Related Information

Stratix V Device Handbook: Known Issues

Lists the planned updates to the

Stratix V Device Handbook

chapters.

Stratix V Family Variants

The Stratix V device family contains the GT, GX, GS, and E variants.

Stratix V GT

devices, with both 28.05-Gbps and 12.5-Gbps transceivers, are optimized for applications

that require ultra-high bandwidth and performance in areas such as 40G/100G/400G optical communica‐

tions systems and optical test systems. 28.05-Gbps and 12.5-Gbps transceivers are also known as GT and

GX channels, respectively.

Stratix V GX

devices offer up to 66 integrated transceivers with 14.1-Gbps data rate capability. These

transceivers also support backplane and optical interface applications. These devices are optimized for

high-performance, high-bandwidth applications such as 40G/100G optical transport, packet processing,

and traffic management found in wireline, military communications, and network test equipment

markets.

Stratix V GS

devices have an abundance of variable precision DSP blocks, supporting up to 3,926 18x18

or 1,963 27x27 multipliers. In addition, Stratix V GS devices offer integrated transceivers with 14.1-Gbps

data rate capability. These transceivers also support backplane and optical interface applications. These

devices are optimized for transceiver-based DSP-centric applications found in wireline, military,

broadcast, and high-performance computing markets.

trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as

trademarks or service marks are the property of their respective holders as described at

www.altera.com/common/legal.html.

Altera warrants performance

of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any

products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,

product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device

specifications before relying on any published information and before placing orders for products or services.

ISO

9001:2008

Registered

www.altera.com

101 Innovation Drive, San Jose, CA 95134

Stratix V Features Summary

SV51001

2015.10.01

Stratix V E

devices offer the highest logic density within the Stratix V family with nearly one million logic

elements (LEs) in the largest device. These devices are optimized for applications such as ASIC and system

emulation, diagnostic imaging, and instrumentation.

Common to all Stratix V family variants are a rich set of high-performance building blocks, including a

redesigned adaptive logic module (ALM), 20 Kbit (M20K) embedded memory blocks, variable precision

DSP blocks, and fractional phase-locked loops (PLLs). All of these building blocks are interconnected by

Altera’s superior multi-track routing architecture and comprehensive fabric clocking network.

Also common to Stratix V devices is the new Embedded HardCopy Block, which is a customizable hard

IP block that leverages Altera’s unique HardCopy ASIC capabilities. The Embedded HardCopy Block in

Stratix V FPGAs is used to harden IP instantiation of PCIe Gen3, Gen2, and Gen1.

Stratix V Features Summary

Table 1: Summary of Features for Stratix V Devices

Feature

Description

Technology

Low-power serial

transceivers

• 28-nm TSMC process technology

• 0.85-V or 0.9-V core voltage

• 28.05-Gbps transceivers on Stratix V GT devices

• Electronic dispersion compensation (EDC) for XFP, SFP+, QSFP, CFP

optical module support

• Adaptive linear and decision feedback equalization

• Transmitter pre-emphasis and de-emphasis

• Dynamic reconfiguration of individual channels

• On-chip instrumentation (EyeQ non-intrusive data eye monitoring)

• 600-Megabits per second (Mbps) to 12.5-Gbps data rate capability

•

1.6-Gbps LVDS

1,066-MHz external memory interface

On-chip termination (OCT)

1.2-V to 3.3-V interfacing for all Stratix V devices

Backplane capability

General-purpose I/Os

(GPIOs)

Embedded HardCopy

Block

Embedded transceiver

hard IP

• PCIe Gen3, Gen2, and Gen1 complete protocol stack, x1/x2/x4/x8 end

point and root port

•

Interlaken physical coding sublayer (PCS)

Gigabit Ethernet (GbE) and XAUI PCS

10G Ethernet PCS

Serial RapidIO

(SRIO) PCS

Common Public Radio Interface (CPRI) PCS

Gigabit Passive Optical Networking (GPON) PCS

Power management

• Programmable Power Technology

• Quartus II integrated PowerPlay Power Analysis

Altera Corporation

Stratix V Device Overview

Send Feedback

SV51001

2015.10.01

Stratix V Family Plan

Feature

Description

High-performance core

fabric

Embedded memory

blocks

Variable precision DSP

blocks

• Enhanced ALM with four registers

• Improved routing architecture reduces congestion and improves compile

times

• M20K: 20-Kbit with hard error correction code (ECC)

• MLAB: 640-bit

• Up to 600 MHz performance

• Natively support signal processing with precision ranging from 9x9 up to

54x54

• New native 27x27 multiply mode

• 64-bit accumulator and cascade for systolic finite impulse responses (FIRs)

• Embedded internal coefficient memory

• Pre-adder/subtractor improves efficiency

• Increased number of outputs allows more independent multipliers

• Fractional mode with third-order delta-sigma modulation

• Integer mode

• Precision clock synthesis, clock delay compensation, and zero delay buffer

(ZDB)

• 800-MHz fabric clocking

• Global, quadrant, and peripheral clock networks

• Unused clock networks can be powered down to reduce dynamic power

•

Serial and parallel flash interface

Enhanced advanced encryption standard (AES) design security features

Tamper protection

Partial and dynamic reconfiguration

Configuration via Protocol (CvP)

Fractional PLLs

Clock networks

Device configuration

High-performance

packaging

• Multiple device densities with identical package footprints enables

seamless migration between different FPGA densities

• FBGA packaging with on-package decoupling capacitors

• Lead and RoHS-compliant lead-free options

—

HardCopy V migration

Stratix V Family Plan

The following tables list the features of the different Stratix V devices.

The information in this section is correct at the time of publication. For the latest information and to get

more details, refer to the Altera Product Selector.

Stratix V Device Overview

Send Feedback

Altera Corporation

Stratix V Family Plan

SV51001

2015.10.01

Table 2: Stratix V GT Device Features

Feature

5SGTC5

5SGTC7

Logic Elements (K)

ALMs

Registers (K)

28.05/12.5-Gbps Transceivers

PCIe hard IP Blocks

Fractional PLLs

M20K Memory Blocks

M20K Memory (MBits)

Variable Precision Multipliers (18x18)

Variable Precision Multipliers (27x27)

DDR3 SDRAM x72 DIMM Interfaces

425

160,400

642

4/32

2,304

512

256

622

234,720

939

4/32

2,560

512

256

User I/Os

(1)

, Full-Duplex LVDS, 28.05/12.5-Gbps Transceivers

Package

(2) (3)

5SGTC5

5SGTC7

KF40-F1517

(4)

(40 mm)

600, 150, 36

(1)

(2)

(3)

(4)

The number of GPIOs does not include transceiver I/Os. In the Quartus II software, the number of user I/

Os includes transceiver I/Os.

Packages are flipchip ball grid array (1.0-mm pitch).

Each package row offers pin migration (common board footprint) for all devices in the row.

Migration between select Stratix V GT devices and Stratix V GX devices is available. For more information,

refer to

Table 6

and to

AN 644: Migration Between Stratix V GX and Stratix V GT Devices.

Stratix V Device Overview

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Altera Corporation

SV51001

2015.10.01

Stratix V Family Plan

Table 3: Stratix V GX Device Features

Features

5SGXA

5SGXB

5SGXBB

Logic

Elements

(K)

ALMs

Registers

(K)

14.1-Gbps

Transceive

PCIe hard

IP Blocks

Fractional

PLLs

M20K

Memory

Blocks

M20K

Memory

(MBits)

Variable

Precision

Multipliers

(18x18)

Variable

Precision

Multipliers

(27x27)

340

420

490

622

840

952

490

597

840

952

128,300 158,500 185,000 234,720 317,000 359,200 185,000 225,400 317,000

513

12, 24,

or 36

1 or 2

(5)

957

634

24 or

1 or 2

1,900

740

24, 36,

or 48

939

24, 36,

or 48

1,268

36 or

1,437

36 or

740

902

1,268

359,200

1,437

1, 2, or 1, 2, or 1, 2, or 1, 2, or

2,304

2,560

2,640

1 or 4

2,100

1 or 4

2,660

1 or 4

2,640

1 or 4

2,640

512

704

798

704

256

352

399

352

(5)

The F1517 package contains 24 PLLs. The other packages with this device contain 20 PLLs.

Altera Corporation

Stratix V Device Overview

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参数对比

与5SGXEA7K2F40C2ESAA相近的元器件有：5SGSMD4H3F35C2NGA、5SGXEA7K2F40C2ESAB。描述及对比如下：

型号	5SGXEA7K2F40C2ESAA	5SGSMD4H3F35C2NGA	5SGXEA7K2F40C2ESAB
描述	FPGA Stratix® V GX Family 622000 Cells 28nm Technology 0.85V 1517-Pin FC-FBGA	FPGA Stratix® V GS Family 360000 Cells 28nm Technology 0.85V 1152-Pin FC-FBGA	FPGA Stratix® V GX Family 622000 Cells 28nm Technology 0.85V 1517-Pin FC-FBGA
欧盟限制某些有害物质的使用	Not Compliant	Compliant with Exemption	Not Compliant
ECCN (US)	3A001.a.7.a	3A991.d	3A001.a.7.a
Part Status	Unconfirmed	Unconfirmed	Unconfirmed
SVHC	Yes	Yes	Yes
SVHC Exceeds Threshold	Yes	Yes	Yes
Family Name	Stratix® V GX	Stratix® V GS	Stratix® V GX
Process Technology	28nm	28nm	28nm
User I/Os	696	432	696
Number of Registers	939000	543000	939000
Operating Supply Voltage (V)	0.85	0.85	0.85
Logic Elements	622000	360000	622000
Number of Multipliers	512 (18x18)	2088 (18x18)	512 (18x18)
Program Memory Type	SRAM	SRAM	SRAM
Embedded Memory (Kbit)	51200	19456	51200
Total Number of Block RAM	2560	957	2560
EMACs	2	2	2
IP Core	Viterbi Compiler, Low-Speed/Hybrid Serial Decoder\|Sub-frame Latency JPEG 2000 Encoder (BA130)\|SPAUI MAC\|RLDRAM II Controller Core\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)	Triple Speed Ethernet with 1588\|DDR4/3, LPDDR2/3 Multiport Memory Controller (UMMC)\|Sub-frame Latency JPEG 2000 Encoder (BA130)	Viterbi Compiler, Low-Speed/Hybrid Serial Decoder\|Sub-frame Latency JPEG 2000 Encoder (BA130)\|SPAUI MAC\|RLDRAM II Controller Core\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)\|RapidIO to AXI Bridge Controller (RAB)
Provider Name	Altera/Barco Silex/Mobiveil, Inc/Commsonic	Altera/Barco Silex/Mobiveil, Inc	Altera/Barco Silex/Mobiveil, Inc/Commsonic
Device Logic Units	622000	360000	622000
Device Number of DLLs/PLLs	28	20	28
Transceiver Channels	48	24	48
Transceiver Speed (Gbps)	14.1	14.1	14.1
Dedicated DSP	256	1044	256
PCIe	4	1	4
Programmability	Yes	Yes	Yes
Reprogrammability Support	Yes	Yes	Yes
Copy Protection	No	No	No
In-System Programmability	Yes	Yes	Yes
Speed Grade	2	2	2
Differential I/O Standards	HCSL\|LVDS\|LVPECL	LVPECL\|LVDS\|HCSL	HCSL\|LVDS\|LVPECL
Single-Ended I/O Standards	LVCMOS\|LVTTL	LVCMOS\|LVTTL	LVCMOS\|LVTTL
External Memory Interface	QDRII+SRAM\|RLDRAM III\|RLDRAM II\|DDR3 SDRAM\|DDR2 SDRAM	DDR2 SDRAM\|DDR3 SDRAM\|RLDRAM II\|RLDRAM III\|QDRII+SRAM	QDRII+SRAM\|RLDRAM III\|RLDRAM II\|DDR3 SDRAM\|DDR2 SDRAM
Minimum Operating Supply Voltage (V)	0.82	0.82	0.82
Maximum Operating Supply Voltage (V)	0.88	0.88	0.88
I/O Voltage (V)	3\|2.5\|1.8\|1.5\|1.35\|1.25\|1.2	1.2\|1.25\|1.35\|1.5\|1.8\|3\|2.5	3\|2.5\|1.8\|1.5\|1.35\|1.25\|1.2
Maximum Operating Temperature (°C)	85	85	85
Supplier Temperature Grade	Commercial	Commercial	Commercial
Supplier Package	FC-FBGA	FC-FBGA	FC-FBGA
Pin Count	1517	1152	1517
Mounting	Surface Mount	Surface Mount	Surface Mount
Package Height	2.7	2.8	2.7
Package Length	40	35	40
Package Width	40	35	40
PCB changed	1517	1152	1517
Shift Registers	Utilize Memory	-	Utilize Memory
Number of Global Clocks	16	-	16
Standard Package Name	BGA	-	BGA
Lead Shape	Ball	-	Ball