IDT5T2010
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK
INDUSTRIAL TEMPERATURE RANGE
2.5V ZERO DELAY PLL
CLOCK DRIVER TERACLOCK™
FEATURES:
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2.5 V
DD
5 pairs of outputs
Low skew: 50ps same pair, 100ps all outputs
Selectable positive or negative edge synchronization
Tolerant of spread spectrum input clock
Synchronous output enable
Selectable inputs
Input frequency: 4.17MHz to 250MHz
Output frequency: 12.5MHz to 250MHz
1.8V / 2.5V LVTTL: up to 250MHz
HSTL / eHSTL: up to 250MHz
Hot insertable and over-voltage tolerant inputs
3-level inputs for selectable interface
3-level inputs for feedback divide selection with multiply ratios
of(1-6, 8, 10, 12)
Selectable HSTL, eHSTL, 1.8V/2.5V LVTTL, or LVEPECL input
interface
Selectable differential or single-ended inputs and ten single-
ended outputs
PLL bypass for DC testing
External differential feedback, internal loop filter
Low Jitter: <75ps cycle-to-cycle
Power-down mode
Lock indicator
Available in BGA and VFQFPN packages
Use replacement parts: 873995AYLF & 873996AYLF
IDT5T2010
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES ON (OCTOBER 28, 2014)
DESCRIPTION:
The IDT5T2010 is a 2.5V PLL clock driver intended for high perfor-
mance computing and data-communications applications. The IDT5T2010
has ten outputs in five banks of two, plus a dedicated differential feedback.
The redundant input capability allows for a smooth change over to a
secondary clock source when the primary clock source is absent.
The feedback bank allows divide-by-functionality from 1 to 12 through
the use of the DS[1:0] inputs. This provides the user with frequency
multiplication 1 to 12 without using divided outputs for feedback. Each output
bank also allows for a divide-by functionality of 2 or 4.
The IDT5T2010 features a user-selectable, single-ended or differential
input to ten single-ended outputs. The clock driver also acts as a translator from
a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended
1.8V/2.5V LVTTL input to HSTL, eHSTL, or 1.8V/2.5V LVTTL outputs.
Selectable interface is controlled by 3-level input signals that may be hard-wired
to appropriate high-mid-low levels. The outputs can be synchronously
enabled/disabled.
Furthermore, when PE is held high, all the outputs are synchronized with
the positive edge of the REF clock input. When PE is held low, all the outputs
are synchronized with the negative edge of REF.
FUNCTIONAL BLOCK DIAGRAM
1sOE
OMODE
TxS
Divide
Select
1
Q
0
1
Q
1
1F
2:1
2sOE
PD
PE
FS
LOCK
PLL_EN
Divide
Select
2
Q
0
2
Q
1
FB
FB/
V
REF2
3
/N
3
PLL
0
3F
2:1
0
1
Divide
Select
4sOE
4
Q
0
4
Q
1
2F
2:1
Divide
Select
3sOE
3
Q
0
3
Q
1
DS
1:0
REF
0
REF
0
/
V
REF0
RxS
1
REF
1
REF
1
/
V
REF1
REF_SEL
4F
2:1
5sOE
Divide
Select
5
Q
0
5
Q
1
5F
2:1
Divide
Select
Q
FB
Q
FB
FBF
2:1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
c
2012
Integrated Device Technology, Inc.
AUGUST 2012
DSC 5981/29
IDT5T2010
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1
A
B
C
D
E
F
G
H
J
K
L
M
V
DD
2
1F
2
3
1sOE
4
1
Q
0
5
1
Q
1
6
GND
7
GND
8
2
Q
1
9
2
Q
0
10
2sOE
11
2F
2
12
V
DDQ
A
B
C
D
E
F
G
H
J
K
L
M
V
DD
V
DD
V
DD
NC
1F
1
GND
GND
2F
1
NC
V
DDQ
V
DDQ
3F
2
OMODE
REF_
SEL
REF
1
V
DD
V
DD
V
DD
GND
GND
GND
GND
V
DDQ
V
DDQ
V
DDQ
3sOE
GND
REF
1
/V
REF1
REF
0
/V
REF0
FB
/V
REF2
PLL_
EN
TxS
V
DD
V
DD
GND
GND
GND
GND
V
DDQ
V
DDQ
NC
3
Q
0
NC
V
DD
GND
GND
GND
GND
V
DDQ
V
DDQ
3F
1
3
Q
1
REF
0
V
DD
V
DD
GND
GND
GND
GND
V
DDQ
V
DDQ
V
DDQ
V
DDQ
FB
V
DD
V
DD
GND
GND
GND
GND
V
DDQ
V
DDQ
V
DDQ
V
DDQ
PD
PE
V
DD
GND
GND
GND
GND
V
DDQ
V
DDQ
4F
1
4
Q
1
RxS
V
DD
V
DD
GND
GND
GND
GND
V
DDQ
V
DDQ
NC
4
Q
0
LOCK
V
DD
V
DD
V
DD
GND
GND
GND
GND
V
DDQ
V
DDQ
V
DDQ
4sOE
V
DD
V
DD
FS
NC
FBF
1
GND
GND
5F
1
NC
V
DDQ
V
DDQ
4F
2
DS
1
DS
0
FBF
2
QFB
QFB
GND
GND
5
Q
1
5
Q
0
5sOE
5F
2
V
DDQ
1
2
3
4
5
6
7
8
9
10
11
12
BGA
TOP VIEW
2
IDT5T2010
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
OMODE
1
sOE
2
Q
1
2
Q
0
1
F
2
2
sOE
V
DDQ
V
DDQ
V
DDQ
V
DD
1
Q
0
1
F
1
2
F
1
V
DDQ
V
DD
1
Q
1
67
59
60
66
63
62
61
65
64
68
58
57
56
55
54
53
52
2
F
2
REF_SEL
V
DD
REF
1
REF
1
/V
REF1
REF
0
REF
0
/V
REF0
FB
FB/V
REF2
V
DD
PE
PD
PLL_EN
V
DD
RxS
TxS
LOCK
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
GND
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
V
DD
3
F
2
3
sOE
V
DDQ
V
DDQ
3
Q
0
3
Q
1
3
F
1
V
DD
4
F
1
4
Q
1
4
Q
0
V
DDQ
V
DDQ
4
sOE
4
F
2
V
DD
26
27
24
25
22
23
21
19
18
20
DS
1
DS
0
FBF
2
FBF
1
5
F
1
28
5
Q
1
29
5
Q
0
30
31
32
33
5
sOE
V
DDQ
V
DDQ
V
DDQ
VFQFPN
TOP VIEW
3
V
DDQ
QFB
QFB
V
DD
5
F
2
FS
34
IDT5T2010
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
DDQ
, V
DD
V
I
V
O
V
REF
T
J
T
STG
Description
Power Supply
Input Voltage
Output Voltage
Reference Voltage
(3)
Junction Temperature
Storage Temperature
Voltage
(2)
Max
–0.5 to +3.6
–0.5 to +3.6
–0.5 to V
DDQ
+0.5
–0.5 to +3.6
150
–65 to +165
Unit
V
V
V
V
°C
°C
CAPACITANCE(TA = +25°C, F = 1MHZ, V
IN
=
0V)
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Min.
2.5
—
Typ.
3
6.3
Max.
3.5
7
Unit
pF
pF
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
DDQ
and V
DD
internally operate independently. No power sequencing requirements
need to be met.
3. Not to exceed 3.6V.
NOTE:
1. Capacitance applies to all inputs except RxS, TxS, nF
[2:1]
, FBF
[2:1]
, and DS
[1:0]
.
RECOMMENDED OPERATING RANGE
Symbol
T
A
V
DD
(1)
V
DDQ
(1)
V
T
Description
Ambient Operating Temperature
Internal Power Supply Voltage
HSTL Output Power Supply Voltage
Extended HSTL and 1.8V LVTTL Output Power Supply Voltage
2.5V LVTTL Output Power Supply Voltage
Termination Voltage
Min.
–40
2.3
1.4
1.65
Typ.
+25
2.5
1.5
1.8
V
DD
V
DDQ
/ 2
Max.
+85
2.7
1.6
1.95
Unit
°C
V
V
V
V
V
NOTE:
1. All power supplies should operate in tandem. If V
DD
or V
DDQ
is at maximum, then V
DDQ
or V
DD
(respectively) should be at maximum, and vice-versa.
PIN DESCRIPTION
I/O
Type
Description
(1)
Clock input. REF
[1:0]
is the "true" side of the differential clock input. If operating in single-ended mode,
I Adjustable
REF
[1:0]
is the clock input.
(1)
Complementary clock input.
REF
[1:0]
/V
REF
[1:0]
is the "complementary" side of REF
[1:0]
if the input is in
REF
[1:0]
/
I Adjustable
differential mode. If operating
V
REF
[1:0]
in single-ended mode,
REF
[1:0]
/V
REF
[1:0]
is left floating. For single-ended
operation in differential mode,
REF
[1:0]
/V
REF
[1:0]
should be set
to the desired toggle voltage for
REF
[1:0]
:
2.5V LVTTL
V
REF
= 1250mV (SSTL2 compatible)
1.8V LVTTL, eHSTL V
REF
= 900mV
HSTL
V
REF
= 750mV
LVEPECL
V
REF
= 1082mV
FB
I Adjustable
(1)
Clock input. FB is the "true" side of the differential feedback clock input. If operating in single-ended mode,
FB is the feedback clock input.
FB/V
REF
2
I Adjustable
(1)
Complementary feedback clock input.
FB/V
REF
2
is the "complementary" side of FB if the input is in
differential mode. If operating in single-ended mode,
FB/V
REF
2
is left floating. For single-ended operation
in differential mode,
FB/V
REF
2
should be set to the desired toggle voltage for FB:
2.5V LVTTL
V
REF
= 1250mV (SSTL2 compatible)
1.8V LVTTL, eHSTL V
REF
= 900mV
NOTE:
HSTL
V
REF
= 750mV
1. Inputs are capable of translating the following interface standards. User can select between:
LVEPECL
V
REF
= 1082mV
Single-ended 2.5V LVTTL levels
Single-ended 1.8V LVTTL levels
or
Differential 2.5V/1.8V LVTTL levels
Differential HSTL and eHSTL levels
Differential LVEPECL levels
Symbol
REF
[1:0]
4
IDT5T2010
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION, CONTINUED
Symbol
REF_SEL
nsOE
I/O
I
I
Type
LVTTL
(1)
LVTTL
(1)
Description
Reference clock select. When LOW, selects REF
0
and
REF
0
/V
REF
0.
When HIGH, selects REF
1
and
REF
1
/
V
REF
1.
Synchronous output enable. When
nsOE
is HIGH, nQ
[1:0]
are synchronously stopped. OMODE selects
whether the outputs are gated LOW/HIGH or tri-stated. When OMODE is HIGH, PE determines the level
at which the outputs stop. When PE is LOW/HIGH, the nQ
[1:0]
is stopped in a HIGH/LOW state. When
OMODE is LOW, the outputs are tri-stated. Set
nsOE
LOW for normal operation.
QFB
QFB
nQ
[1:0]
RxS
TxS
PE
nF
[2:1]
FBF
[2:1]
FS
DS
[1:0]
PLL_EN
PD
O Adjustable
(2)
Feedback clock output
O Adjustable
(2)
Complementary feedback clock output
O Adjustable
(2)
Five banks of two outputs
I
I
I
I
I
I
I
I
I
3-Level
(3)
3-Level
(3)
LVTTL
(1)
LVTTL
(1)
LVTTL
(1)
LVTTL
(1)
3-Level
(3)
LVTTL
(1)
LVTTL
(1)
Selects single-ended 2.5V LVTTL (HIGH), 1.8V LVTTL (MID) REF clock input or differential (LOW) REF
clock input
Sets the drive strength of the output drivers and feedback inputs to be 2.5V LVTTL (HIGH), 1.8V LVTTL
(MID) or HSTL/eHSTL (LOW) compatible. Used in conjuction with V
DDQ
to set the interface levels.
Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive
edge of the reference clock (has internal pull-up).
Function select inputs for divide-by-2, divide-by-4, zero delay, or invert on each bank (See Control Summary table)
Function select inputs for divide-by-2, divide-by-4, zero delay, or invert on the feedback bank (See Control Summary table)
Selects appropriate oscillator circuit based on anticipated frequency range. (See VCO Frequency Range Select.)
3-level inputs for feedback input divider selection (See Divide Selection table)
PLL enable/disable control. Set LOW for normal operation. When
PLL_EN
is HIGH, the PLL is disabled and REF
[1:0]
goes
to all outputs.
Power down control. When
PD
is LOW, the inputs are disabled and internal switching is stopped. OMODE selects whether
the outputs are gated LOW/HIGH or tri-stated. When OMODE is HIGH, PE determines the level at which the outputs stop.
When PE is LOW/HIGH, the nQ
[1:0]
and QFB are stopped in a HIGH/LOW state, while the
QFB
is stopped in a LOW/HIGH
state. When OMODE is LOW, the outputs are tri-stated. Set
PD
HIGH for normal operation.
PLL lock indication signal. HIGH indicates lock. LOW indicates that the PLL is not locked and outputs may not be
synchronized to the inputs. The output will be 2.5V LVTTL. (For more information on application specific use of the LOCK
pin, please see AN237.)
Output disable control. Determines the outputs' disable state. Used in conjunction with
nsOE
and
PD.
(See Output Enable/
LOCK
O
LVTTL
NOTES:
Disable and
signals under all conditions. If the output is operating at 1.8V or 1.5V, the LVTTL inputs will accept 1.8V
1. Pins listed as LVTTL inputs will accept 2.5V
Powerdown tables.)
LVTTL signals as well.
PWR
V
DDQ
Power supply for output buffers. When using 2.5V LVTTL, V
DDQ
should be connected to V
DD.
2. Outputs are user selectable to drive 2.5V, 1.8V LVTTL, eHSTL, or HSTL interface levels when used with the appropriate V
DDQ
voltage.
V
DD
PWR
Power supply for phase locked loop, lock output, inputs, and other internal circuitry
3. 3-level inputs are static inputs and must be tied to V
DD
or GND or left floating. These inputs are not hot-insertable or over voltage tolerant.
OMODE
I
LVTTL
(1)
OUTPUT ENABLE/DISABLE
GND
PWR
Ground
nsOE
L
H
H
OMODE
X
L
H
Output
Normal Operation
Tri-State
Gated
(1)
VCO FREQUENCY RANGE SELECT
FS
(1)
LOW
HIGH
Min.
50
100
Max.
125
250
Unit
MHz
MHz
NOTE:
1. PE determines the level at which the outputs stop. When PE is LOW/HIGH, the
nQ
[1:0]
is stopped in a HIGH/LOW state.
POWERDOWN
PD
H
L
L
OMODE
X
L
H
Output
Normal Operation
Tri-State
Gated
(1)
NOTE:
1. The level to be set on FS is determined by the nominal operating frequency of the
VCO. The VCO frequency (F
NOM
) always appears at nQ
[1:0]
outputs when they are
operated in their undivided modes. The frequency appearing at the REF
[1:0]
and
REF
[1:0]
/V
REF[1:0]
and FB and
FB/V
REF
2 inputs will be F
NOM
when the QFB and
QFB
are undivided and DS
[1:0]
= MM. The frequency of REF
[1:0]
and
REF
[1:0]
/V
REF[1:0]
and FB and
FB/V
REF
2 inputs will be F
NOM
/2 or F
NOM
/4 when the part is configured for
frequency multiplication by using a divided QFB and
QFB
and setting DS
[1:0]
= MM.
Using the DS
[1:0]
inputs allows a different method for frequency multiplication (see
Divide Selection table).
NOTE:
1. PE determines the level at which the outputs stop. When PE is LOW/HIGH, the
nQ
[1:0]
and QFB are stopped in a HIGH/LOW state, while the
QFB
is stopped in a
LOW/HIGH state.
5
