Model 638
Features
Ultra Low Jitter LVPECL or LVDS Clock
Ceramic Surface Mount Package
Ultra Low Phase Jitter Performance, 100fs Typical
Fundamental or 3
rd
Overtone Crystal Design
Frequency Range 80 – 170MHz *
+2.5V or +3.3V Operation
Output Enable Standard
Tape and Reel Packaging, EIA-418
SerDes
Storage Area Networking
Broadband Access
SONET/SDH/DWDM
PON
Ethernet/GbE/SyncE
Fiber Channel
Test and Measurement
Part Dimensions:
7.0 × 5.0 × 2.0mm
•
178.462mg
Applications
Standard Frequencies, 100fs Maximum
- 125.00MHz
- 156.25MHz
- 150.00MHz
- 156.2539MHz
- 155.52MHz
- 161.1328MHz
* See Page 8 for additional developed frequencies.
Check with factory for availability of frequencies
l d
Description
CTS Model 638 is a low cost, high performance clock oscillator supporting differential LVPECL or LVDS outputs.
Employing the latest IC technology, M638 has excellent stability and low jitter/phase noise performance.
Ordering Information
Model
638
Output Type
P
Frequency Code
[MHz]
XXX or XXXX
Frequency
Stability
3
Temperature
Range
I
Supply
Voltage
3
Packaging
T
Code
P
L
E
V
Output
LVPECL - Pin 1 Enable
LVDS - Pin 1 Enable
LVPECL - Pin 2 Enable
LVDS - Pin 2 Enable
Code
6
5
3
2
Stability
±20ppm
±25ppm
±50ppm
±100ppm
2
Code
2
3
Voltage
+2.5Vdc
+3.3Vdc
Code
Frequency
Product Frequency Code
1
Code Temp. Range
-10°C to +60°C
A
-20°C to +70°C
C
-40°C to +85°C
I
Packing
Code
1k pcs./reel
T
Notes:
1] Refer to document 016-1454-0, Frequency Code Tables. 3-digits for frequencies <100MHz, 4-digits for frequencies 100MHz or greater.
2] Consult factory for availability of 6I Stability/Temperature combination.
Not all performance combinations and frequencies may be available.
Contact your local CTS Representative or CTS Customer Service for availability.
This product is specified for use only in standard commercial applications. Supplier disclaims all express and implied warranties and liability in connection with any use of this
product in any non-commercial applications or in any application that may expose the product to conditions that are outside of the tolerances provided in its specification.
DOC# 008-0539-0 Rev. C
Page 1 of 8
©2017 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Ultra Low Jitter LVPECL or LVDS Clock
Model 638
Electrical Specifications
Operating Conditions
P ARAMETER
Maximum Supply Voltage
Supply Voltage
Supply Current
LVP ECL
LVDS
O perating Temperature
Storage Temperature
T
A
T
STG
-
-
I
CC
Maximum Load
-
-
-20
-40
-40
55
45
+25
-
88
66
+70
+85
+125
mA
°C
°C
SYMBO L
V
CC
V
CC
CO NDITIO NS
-
±5%
MIN
-0.5
2.375
3.135
TYP
-
2.5
3.3
MAX
5.0
2.625
3.465
UNIT
V
V
Frequency Stability
P ARAMETER
Frequenc y Range
LVP ECL
LVDS
Frequenc y Stability
[Note 1]
SYMBO L
f
O
CO NDITIO NS
-
MIN
TYP
80 - 170
80 - 170
MAX
UNIT
MHz
±ppm
3
ppm
Δf/f
O
Δf/f
25
-
First Year @ +25°C, nominal V
CC
-3
20, 25, 50 or 100
-
Aging
1.] Inclusive of initial tolerance at time of shipment, changes in supply voltage, load, temperature and 1st year aging.
Output Parameters
P ARAMETER
O utput Type
O utput Load
SYMBO L
-
R
L
V
OH
O utput Voltage Levels
V
OL
V
OH
V
OL
O utput Duty Cyc le
Rise and Fall Time
O utput Type
O utput Load
O utput Voltage Levels
O utput Duty Cyc le
Differential O utput Voltage
O ffset Voltage
Rise and Fall Time
SYM
T
R
, T
F
-
R
L
V
OH
V
OL
SYM
V
OD
V
OS
T
R
, T
F
CO NDITIO NS
-
Terminated to V
CC
- 2.0V
PECL Load, -20°C to +70°C
PECL Load, -40°C to +85°C
@ V
CC
- 1.3V
@ 20%/80% Levels, R
L
= 50 Ohms
-
Between Outputs
LVDS Load
@ 1.25V
R
L
= 100 Ohms
LVDS Load
@ 20%/80% Levels, R
L
= 100 Ohms
-
-
0.90
45
247
1.125
-
-
V
CC
- 1.025
V
CC
- 1.810
V
CC
- 1.085
V
CC
- 1.830
45
-
MIN
TYP
LVP ECL
50
-
-
-
-
-
0.3
LVDS
100
1.43
1.10
-
330
1.25
0.4
-
1.60
-
55
454
1.375
0.7
-
V
CC
- 0.880
V
CC
- 1.620
V
CC
- 0.880
V
CC
- 1.555
55
0.7
MAX
UNIT
-
Ohms
V
V
%
ns
-
Ohms
V
%
mV
V
ns
DOC# 008-0539-0 Rev. C
Page 2 of 8
©2017 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Ultra Low Jitter LVPECL or LVDS Clock
Model 638
Electrical Specifications
Output Parameters
P ARAMETER
Start Up Time
Enable Func tion [Standby]
Enable Input Voltage
Disable Input Voltage
Disable Time
Enable Time
P hase Jitter, RMS
P eriod Jitter, pk-pk
P eriod Jitter, RMS
V
IH
V
IL
T
PLZ
T
PLZ
tjrms
pjpk-pk
pjrms
Pin 1 or 2 Logic '1', Output Enabled
Pin 1 or 2 Logic '0', Output Disabled
Pin 1 or 2 Logic '0', Output Disabled
Pin 1 or 2 Logic '1', Output Enabled
80 - 124.9MHz, Bandwidth 12 kHz - 20 MHz
125 - 170MHz, Bandwidth 12 kHz - 20 MHz
-
-
-
-
0.7V
CC
-
-
-
-
-
-
-
-
-
-
2.6
25
-
0.3V
CC
200
2
200
100
-
-
V
V
ns
ms
fs
fs
ps
ps
SYMBO L
T
S
CO NDITIO NS
Application of V
CC
MIN
-
TYP
2
MAX
5
UNIT
ms
Enable Truth Table
Pin 1 or Pin 2
Logic ‘1’
Open
Logic ‘0’
Pin 4 & Pin 5
Output
Output
High Imp.
Test Circuit
LVPECL
LVDS
Output Waveform
LVPECL or LVDS
DOC# 008-0539-0 Rev. C
Page 3 of 8
©2017 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Ultra Low Jitter LVPECL or LVDS Clock
Model 638
Electrical Specifications
Performance Data
Phase Noise [typical]
125.00MHz, LVPECL, V
CC
= 3.3V, T
A
= +25°C
156.25MHz, LVPECL, V
CC
= 3.3V, T
A
= +25°C
DOC# 008-0539-0 Rev. C
Page 4 of 8
©2017 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Ultra Low Jitter LVPECL or LVDS Clock
Model 638
Electrical Specifications
Performance Data
Phase Noise [typical]
156.25MHz, LVDS, V
CC
= 3.3V, T
A
= +25°C
Phase Noise Tabulated
Typical, V
CC
= 3.3V, T
A
= +25°C
P ARAMETER
LVP ECL @ 1 2 5 .0 0 MHz
P hase Noise
Single Side Band
@ 10Hz
@ 100Hz
-
@ 1kHz
@ 10kHz
@ 100kHz
@ 1MHz
@ 5MHz
P hase Jitter, RMS
P ARAMETER
LVDS @ 1 5 6 .2 5 MHz
P hase Noise
Single Side Band
@ 10Hz
@ 100Hz
-
@ 1kHz
@ 10kHz
@ 100kHz
@ 1MHz
@ 20MHz
P hase Jitter, RMS
tjrms
Integration Bandwidth 12kHz - 20MHz
-71.41
-103.93
-128.68
-145.73
-155.28
-154.78
-157.92
82.99
fs
dBc/Hz
tjrms
SYMBO L
Integration Bandwidth 12kHz - 20MHz
CO NDITIO NS
-79.62
-107.25
-135.31
-146.45
-151.59
-152.31
-153.73
89.77
TYP
fs
UNIT
P hase Jitter, RMS
tjrms
dBc/Hz
-
SYMBO L
CO NDITIO NS
TYP
UNIT
P ARAMETER
LVP ECL @ 1 5 6 .2 5 MHz
P hase Noise
Single Side Band
@ 10Hz
@ 100Hz
@ 1kHz
@ 10kHz
@ 100kHz
@ 1MHz
@ 20MHz
Integration Bandwidth 12kHz - 20MHz
-75.60
-103.54
-132.26
-149.09
-155.26
-155.33
-158.39
77.86
fs
dBc/Hz
SYMBO L
CO NDITIO NS
TYP
UNIT
DOC# 008-0539-0 Rev. C
Page 5 of 8
©2017 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
