Model 654P/L
Features
Ceramic Surface Mount Package
Low Phase Jitter Performance, 600fs Typical
Advanced PLL Design w/ Low Fundamental Crystal
Frequency Range 10MHz – 1.0GHz *
+2.5V or +3.3V Operation
Output Enable Standard
Tape and Reel Packaging, EIA‐418
Advanced PLL LVPECL or LVDS Clock
Part Dimensions:
5.0 × 3.2 × 1.2mm • 62.00mg
Applications
Broadcast Video
Storage Area Networking
Broadband Access
PCI Express
Networking Equipment
Ethernet/GbE/SyncE
Fiber Channel
Test and Measurement
Standard Frequencies
‐ 25.00MHz
‐ 27.00MHz
‐ 125.00MHz
‐ 155.52MHz
‐ 161.1328MHz
‐ 622.08MHz
‐ 644.53125MHz
‐ 693.4830MHz
* Check with factory for availability.
Description
CTS Model 654P/L is a low cost, high performance PLL clock oscillator supporting differential LVPECL or LVDS
outputs. Employing the latest IC technology, M654P/L has excellent stability and low phase jitter performance.
Ordering Information
Model
654
Output
Type
P
Frequency Code
[MHz]
X XX
or XXX
X
Frequency
Stability
3
Temperature
Range
I
Supply
Voltage
3
Packaging
T
Code
Frequency
1
Product Frequency Code
Code Temp. Range
‐20°C to +70°C
C
‐40°C to +85°C
I
Packing
Code
1k pcs./reel
T
Code
P
L
Output
LVPECL
LVDS
Code
6
5
3
Stability
±20ppm
±25ppm
±50ppm
2
Code
2
3
Voltage
+2.5Vdc
+3.3Vdc
Notes:
1] Refer to document 016‐1454‐0, Frequency Code Tables.
3‐digits for frequencies <100MHz, 4‐digits for frequencies 100MHz or greater.
2] Consult factory for availability of 6I Stability/Temperature combination.
Not all performance combinations and frequencies may be available.
Contact your local CTS Representative or CTS Customer Service for availability.
DOC# 008‐0549‐0 Rev. B
Page 1 of 7
©2015 CTS® Corporation.
Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 654P/L
Advanced PLL LVPECL or LVDS Clock
Electrical Specifications
Operating Conditions
P
ARAMETER
Maximum Supp
ly Voltage
Sup
ply Voltage
Sup
ply Current
LVP
ECL
LVDS
O
peratin g Temperature
Sto
rage Temperature
T
A
T
STG
‐
‐
I
CC
Maximum Load
‐
‐
‐20
‐40
‐55
54
23
+25
‐
‐
‐
+70
+85
+125
mA
SYMBO L
V
CC
V
CC
CO NDITIO NS
‐
±5%
MIN
‐0.5
2.375
3.135
TYP
‐
2.5
3.3
MAX
5.0
2.625
3.465
UNIT
V
V
°C
°C
Frequency Stability
P
ARAMETER
Frequenc
y Ran ge
Frequenc
y Stability
[Note 1]
SYMBO L
f
O
Δf/f
O
Δf/f
25
CO NDITIO NS
‐
‐
First Year @ +25°C, nominal V
CC
MIN
TYP
10 ‐ 1000
20, 25 or 50
MAX
UNIT
MHz
±ppm
Aging
‐3
‐
3
ppm
1.] Inc lusive of initial tolerance at time of shipment, c hanges in supply voltage, load, temperature and 1st year aging.
Output Parameters
P
ARAMETER
O
utput Ty pe
O
utput Load
O
utput Voltage Levels
O
utput Duty
Cy
c le
Rise and Fall Time
SYMBO L
‐
R
L
V
OH
V
OL
SYM
T
R
, T
F
CO NDITIO NS
‐
Terminated to V
CC
‐ 2.0V
PECL Load
@ V
CC
‐ 1.3V
@ 20%/80% Levels, R
L
= 50 Ohms
‐
V
CC
‐ 1.03
V
CC
‐ 1.85
45
‐
MIN
TYP
LVPECL
50
‐
‐
‐
0.25
LVDS
‐
‐
0.90
45
175
1.20
‐
100
1.43
1.10
‐
350
1.25
‐
‐
1.60
‐
55
454
1.30
0.4
‐
V
CC
‐ 0.60
V
CC
‐ 1.60
55
0.60
MAX
UNIT
‐
Ohms
V
%
ns
O
utput Ty pe
O
utput Load
O
utput Voltage Levels
O
utput Duty
Cy
c le
Differential O
utput Voltage
O
ffset Voltage
Rise and Fall Time
‐
R
L
V
OH
V
OL
SYM
V
OD
V
OS
T
R
, T
F
‐
Between Outputs
LVDS Load
@ 1.25V
R
L
= 100 Ohms
LVDS Load
@ 20%/80% Levels, R
L
= 100 Ohms
‐
Ohms
V
%
mV
V
ns
DOC# 008‐0549‐0 Rev. B
Page 2 of 7
©2015 CTS® Corporation.
Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 654P/L
Advanced PLL LVPECL or LVDS Clock
Electrical Specifications
Output Parameters
P
ARAMETER
Start Up Time
Enable Func
tion [Standby ]
Enable Input Voltage
Disable Input Voltage
Disable Current
Enable Time
P
hase Jitter, RMS
P
eriod Jitter, pk‐pk
P
eriod Jitter, RMS
V
IH
V
IL
I
IL
T
PLZ
tjrms
pjpk‐pk
pjrms
Pin 1 Logic '1', Output Enabled
Pin 1 Logic '0', Output Disabled
Pin 1 Logic '0', Output Disabled
Pin 1 Logic '1', Output Enabled
Bandwidth 12 kHz ‐ 20 MHz
‐
‐
0.7V
CC
‐
‐
‐
‐
‐
‐
‐
‐
‐
‐
600
2.5
25
‐
0.3V
CC
20
5
<1000
‐
‐
V
V
uA
ns
fs
ps
ps
SYMBO L
T
S
CO NDITIO NS
Application of V
CC
MIN
‐
TYP
3
MAX
5
UNIT
ms
Enable Truth Table
Pin 1
Logic ‘1’
Open
Logic ‘0’
Pin 4 & Pin 5
Output
Output
High Imp.
Test Circuit
LVPECL
LVDS
Output Waveform
LVPECL or LVDS
DOC# 008‐0549‐0 Rev. B
Page 3 of 7
©2015 CTS® Corporation.
Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 654P/L
Advanced PLL LVPECL or LVDS Clock
Electrical Specifications
Performance Data
Phase Noise [typical]
100.00MHz, LVPECL, V
CC
= 3.3V, T
A
= +25°C
156.25MHz, LVPECL, V
CC
= 3.3V, T
A
= +25°C
312.50MHz, LVPECL, V
CC
= 3.3V, T
A
= +25°C
800.00MHz, LVPECL, V
CC
= 3.3V, T
A
= +25°C
DOC# 008‐0549‐0 Rev. B
Page 4 of 7
©2015 CTS® Corporation.
Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 654P/L
Advanced PLL LVPECL or LVDS Clock
Performance Data
Phase Noise Tabulated
Typical, HCMOS, V
CC
= 3.3V, T
A
= +25°C
P
ARAMETER
LVP ECL @
1
0 0 .0 0 MHz
P
h ase No ise
Single Side Band
@ 10Hz
@ 100Hz
@ 1kHz
‐
@ 10kHz
@ 100kHz
@ 1MHz
@ 10MHz
@ 40MHz
P
h ase Jitter, RMS
tjrms
‐69.70
‐92.90
‐115.90
‐126.80
dBc/Hz
‐129.50
‐143.50
‐154.90
‐155.30
fs
P
hase Jitter, RMS
tjrms
‐
SYMBO L
CO NDITIO NS
TYP
UNIT
P
ARAMETER
LVP ECL @
1
5 6 .2 5 MHz
P
hase Noise
Single Side Band
@ 10Hz
@ 100Hz
@ 1kHz
@ 10kHz
@ 100kHz
@ 1MHz
@ 10MHz
@ 40MHz
‐88.60
‐97.80
‐111.40
‐121.00
dBc/Hz
‐127.00
‐141.80
‐151.50
‐153.30
fs
SYMBO L
CO NDITIO NS
TYP
UNIT
Integration Bandwidth 12kHz ‐ 20MHz
714.35
Integration Bandwidth 12kHz ‐ 20MHz
869.93
P
ARAMETER
LVP ECL @
3
1 2 .5 0 MHz
P
h ase No ise
SYMBO L
CO NDITIO NS
TYP
UNIT
P
ARAMETER
LVP ECL @
8
0 0 .0 0 MHz
SYMBO L
CO NDITIO NS
TYP
UNIT
Single Side Band
@ 10Hz
@ 100Hz
@ 1kHz
‐
@ 10kHz
@ 100kHz
@ 1MHz
@ 10MHz
@ 40MHz
‐81.30
‐91.80
‐105.30
‐115.50
dBc/Hz
‐120.80
‐136.40
‐153.20
‐153.20
fs
P
hase Noise
Single Side Band
@ 10Hz
@ 100Hz
@ 1kHz
‐
@ 10kHz
@ 100kHz
@ 1MHz
@ 10MHz
@ 40MHz
‐85.00
‐90.90
‐96.90
‐106.70
dBc/Hz
‐107.50
‐125.90
‐145.40
‐150.40
fs
P
h ase Jitter, RMS
tjrms
Integration Bandwidth 12kHz ‐ 20MHz
496.03
P
hase Jitter, RMS
tjrms
Integration Bandwidth 12kHz ‐ 20MHz
781.63
DOC# 008‐0549‐0 Rev. B
Page 5 of 7
©2015 CTS® Corporation.
Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
DSP 与 ARM 处理器
