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658L5C2750M0000

LVDS Output Clock Oscillator, 750MHz Nom, GREEN, CERAMIC PACKAGE-6

器件类别:无源元件    振荡器   

厂商名称:CTS

器件标准:  

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器件参数
参数名称
属性值
是否无铅
不含铅
是否Rohs认证
符合
厂商名称
CTS
包装说明
GREEN, CERAMIC PACKAGE-6
Reach Compliance Code
compliant
其他特性
ENABLE/DISABLE FUNCTION; COMPLIMENTARY OUTPUT; TAPE AND REEL
最长下降时间
1 ns
频率调整-机械
NO
频率稳定性
25%
JESD-609代码
e4
安装特点
SURFACE MOUNT
标称工作频率
750 MHz
最高工作温度
70 °C
最低工作温度
振荡器类型
LVDS
输出负载
100 OHM
物理尺寸
7.0mm x 5.0mm x 2.0mm
最长上升时间
1 ns
最大供电电压
2.63 V
最小供电电压
2.38 V
标称供电电压
2.5 V
表面贴装
YES
最大对称度
55/45 %
端子面层
Gold (Au) - with Nickel (Ni) barrier
文档预览
Model 658
CLOCK, HIGH FREQUENCY MULTIPLIER
FEATURES
Standard 7x5mm Surface Mount Footprint
LVCMOS, Differential LVPECL or LVDS Outputs
Frequency Range 38 – 750 MHz
Frequency Stability, ±50 ppm Standard
(± 25 ppm and ± 100 ppm available)
+2.5Vdc or +3.3Vdc Operation
Operating Temperature to –40°C to +85°C
Output Enable Standard
Low Phase Jitter,
PLL Multiplier
Tape & Reel Packaging
RoHS/Green Compliant
DESCRIPTION
The Model 658 is a ceramic packaged Clock
oscillator offering reduced size and enhanced
stability. The small size means it is perfect for
any application. The enhanced stability means it
is the perfect choice for today’s communications
applications that require tight frequency control.
ORDERING INFORMATION
658
OUTPUT TYPE
C = CMOS,
Pin 1 Enable Pin 2 N.C. (standard)
L = LVDS,
Pin 1 Enable Pin 2 N.C. (standard)
P = PECL,
Pin 1 Enable Pin 2 N.C. (standard)
M = CMOS,
Pin1 N.C. Pin 2 Enable
V = LVDS,
Pin1 N.C. Pin 2 Enable
E = PECL,
Pin1 N.C. Pin 2 Enable
FREQUENCY STABILITY
5 = ± 25 ppm
3 = ± 50 ppm (standard)
2 = ± 100 ppm
M
FREQUENCY IN MHz
M - indicates MHz and decimal point.
Frequency is recorded with minimum 4
significant digits to the right of the "M".
SUPPLY VOLTAGE
2 = 2.5 Vdc (LVDS and PECL only)
3 = 3.3 Vdc
OPERATING TEMPERATURE RANGE
C = 0°C to +70°C (standard)
I = -40°C to +85°C
Example Part Number: 658P3C3155M5200
Document No. 008-0316-0
Page 1 - 5
Rev. A
٠ ٠ ٠
CTS Electronic Components, Inc.
٠
171 Covington Drive
٠
Bloomingdale, IL 60108
٠ ٠ ٠
٠ ٠ ٠
www.ctscorp.com
٠ ٠ ٠
7x5mm Low Cost
LVCMOS, LVPECL or LVDS Clock
Model 658
ELECTRICAL CHARACTERISTICS
PARAMETER
Maximum Supply Voltage
Absolute Maximums
Storage Temperature
Frequency Range
LVCMOS
LVPECL and LVDS
(See Note 1 and Ordering Information)
SYMBOL
V
CC
T
STG
f
O
∆f/f
O
T
A
V
CC
±5%
CONDITIONS
-
-
-
MIN
-0.5
-55
50
38
-
0
-40
2.38
3.14
< 160 MHz
160 MHz
-
-
-
-
-
-
-
-
0.7*V
CC
-
-
-
-
TYP
-
-
-
-
-
MAX
7.0
125
250
750
25, 50 or
100
70
85
2.63
3.47
40
50
75
100
60
80
10
5
-
0.3*V
CC
20
10
15
55
-
10%V
CC
5.0
-
55
-
V
CC
- 1.62V
1.0
-
55
450
1.6
-
1.0
UNIT
V
°C
MHz
Frequency Stability
-
-
± ppm
°C
Operating Temperature
Commercial
Industrial
(See Ordering Information)
25
2.5
3.3
-
-
-
-
-
-
-
3.5
-
-
-
5
-
-
-
-
2
50
-
-
-
0.4
Supply Voltage
Supply Current
LVCMOS
LVPECL
LVDS
Start Up Time
Phase Jitter
V
Maximum Load
I
CC
< 160 MHz
160 MHz
< 160 MHz
160 MHz
mA
T
S
tjms
V
IH
V
IL
I
IL
T
PLZ
C
L
SYM
V
OH
V
OL
T
R
, T
F
R
L
SYM
V
OH
V
OL
T
R
, T
F
R
L
SYM
V
OD
V
OH
V
OL
T
R
, T
F
Application of V
CC
Bandwidth 12 kHz - 20 MHz
Pin 1 or Pin 2 Logic '1', Output Enabled
Pin 1 or Pin 2 Logic '0', Output Disabled
Pin 1 or Pin 2 Logic '1' , Output Disabled
Pin 1 or Pin 2 Logic '1'
ms
ps RMS
V
uA
ms
pF
%
V
ns
Ohms
%
V
ns
Ohms
%
mV
V
ns
Enable Function
Enable Input Voltage
Electrical and Waveform Parameters
Disable Input Voltage
Disable Current
Enable Time
LVCMOS WAVEFORM
Output Load
Output Duty Cycle
Output Voltage Levels
Logic '1' Level
Logic '0' Level
Rise and Fall Time
LVPECL WAVEFORM
Output Load
Output Duty Cycle
Output Voltage Levels
Logic '1' Level
Logic '0' Level
Rise and Fall Time
LVDS WAVEFORM
Output Load
Output Duty Cycle
Differential Voltage
Output Voltage Levels
Logic '1' Level
Logic '0' Level
Rise and Fall Time
@ 50% Level
CMOS Load
CMOS Load
@ 20% - 80% Levels
-
@ V
CC
- 1.3V
PECL Load
PECL Load
@ 20% - 80% Levels
-
@ 1.25V
RL = 100 Ohms
LVDS Load
LVDS Load
@ 20% - 80% Levels
45
90%V
CC
-
-
-
45
V
CC
- 1.025V
-
-
45
250
-
0.9
-
100
-
350
-
-
0.4
Notes:
1. Inclusive of initial tolerance at time of shipment, changes in supply voltage, load, temperature and 10 year aging
at an average operating temperature of +40 °C.
Document No. 008-0316-0
Page 2 - 5
Rev. A
٠ ٠ ٠
CTS Electronic Components, Inc.
٠
171 Covington Drive
٠
Bloomingdale, IL 60108
٠٠٠
7x5mm Low Cost
LVCMOS, LVPECL or LVDS Clock
CMOS/TTL OUTPUT WAVEFORM
TEST CIRCUIT, CMOS LOAD
Model 658
Tr
Tf
N.C.
V
OH
90%, 80%, 2.4V
+
mA
-
6
5
D.U.T.
4
C
L
3
Including probe
capacitance.
50%, 1.5V
+
POWER
SUPPLY
+
VM
-
0.01uF
10%, 20%, 0.5V
UPTIME (t)
PERIOD (T)
-
1
2
V
OL
DUTY CYCLE = t/T x 100 (%)
Enable Input or N.C.
N.C. or Enable Input
PECL/LVDS OUTPUT WAVEFORM
Tr
Tf
TEST CIRCUIT, PECL LOAD
Vcc - 2.0V
OUT
V
OH
80%
R
L
50
CH2
V
OS
50%
+
mA
-
R
L
50
Vcc - 2.0V
3
CH1
6
5
D.U.T.
1
2
4
20%
OUT
UPTIME (t)
PERIOD (T)
+
POWER
SUPPLY
+
VM
-
0.01uF
V
OL
-
DUTY CYCLE = t/T x 100 (%)
Enable Input or N.C.
N.C. or Enable Input
TEST CIRCUIT, LVDS LOAD
D.U.T. PIN ASSIGNMENTS
PIN
1
2
3
4
5
6
SYMBOL
EOH / NC
NC / EOH
GND
Output
Output / NC
V
CC
DESCRIPTION
Enable or No Connect
No Connect or Enable
Circuit & Package Ground
RF Output
Complimentary RF Output
(PECL and LVDS Only)
CH2
R
L
100
CH1
6
+
POWER
SUPPLY
+
mA
-
5
D.U.T.
4
+
VM
-
0.01uF
Supply Voltage
-
1
2
3
ENABLE TRUTH TABLE
PIN 1 or 2
Logic ‘1’
Open
Logic ‘0’
PIN 4 / PIN 5
Output
Output
High Imp.
Enable Input or N.C.
N.C. or Enable Input
Document No. 008-0316-0
Page 3 - 5
Rev. A
٠ ٠ ٠
CTS Electronic Components, Inc.
٠
171 Covington Drive
٠
Bloomingdale, IL 60108
٠٠٠
7x5mm Low Cost
LVCMOS, LVPECL or LVDS Clock
Model 658
MECHANICAL SPECIFICATIONS
PACKAGE DRAWING
(7.0 ±0.2)
0.276 ±0.008
PIN 1 IDENTIFIER
(1.4)
0.055
(1.27)
0.050
(5.0 ±0.2)
0.197 ±0.008
(3.73)
0.147
4
5
6
MARKING INFORMATION
1.
2.
3.
4.
** - Manufacturing Site Code.
YYWW – Date code, YY – year, WW – week.
Truncated CTS part number.
XXXMXXXX - Frequency marked with 4
significant digits after the ‘M’.
CTS ** YYWW
658P3C3
XXXMXXXX
3
2
1
(2.54)
0.100
(2.0)
MAX
0.079
(5.08)
0.200
Key:
(mm)
Inch
NOTES
1. Termination pads (e4), barrier-plating is nickel
(Ni) with gold (Au) flash plate.
2. Reflow conditions per JEDEC J-STD-020.
SUGGESTED SOLDER PAD GEOMETRY
.071 [1.80]
300
SUGGESTED REFLOW PROFILE
C
BYPASS
6
5
4
200
Maximum 260°C, 10 seconds
Typical 245°C
.165 [4.20]
Temp.
(°C)
100
130°C
.079 [2.00]
1
2
.100 [2.54]
.200 [5.08]
Key:
[mm]
Inch
3
0
0
30
60
90
120
150
180
210
240
270
300
Time (Seconds)
C
BYPASS
should be
0.01 uF.
Document No. 008-0316-0
Page 4 - 5
Rev. A
٠ ٠ ٠
CTS Electronic Components, Inc.
٠
171 Covington Drive
٠
Bloomingdale, IL 60108
٠٠٠
7x5mm Low Cost
LVCMOS, LVPECL or LVDS Clock
Model 658
TAPE AND REEL INFORMATION
DIMENSIONS IN MILLIMETERS
17.5
Ø13
4.0
8.0
Ø1.50
1.75
2.40
2.10
2.0
120°
8.40
7.90
16.0
Ø60
Ø180
5.70
5.40
DIRECTION OF FEED
Ø23
Device quantity is 1,000 pieces per 180mm reel.
ENVIRONMENTAL SPECIFICATIONS
Temperature Cycle:
Mechanical Shock:
Sinusoidal Vibration:
Gross Leak:
Fine Leak:
Resistance to Solder Heat:
High Temperature Operating Bias:
Frequency Aging:
Moisture Sensitivity Level:
400 cycles from –55°C to +125°C, 10 minute dwell at each temperature, 1
minute transfer time between temperatures.
1,500g’s, 0.5mS duration, ½ sinewave, 3 shocks each direction along 3
mutually perpendicular planes (18 total shocks).
0.06 inches double amplitude, 10 to 55 Hz and 20g’s, 55 to 2,000 Hz, 3 cycles
each in 3 mutually perpendicular planes (9 times total).
No leak shall appear while immersed in an FC40 or equivalent liquid at
+125°C for 20 seconds.
Mass spectrometer leak rates less than 2x10
-8
ATM cc/sec air equivalent.
Product must survive 3 reflows of +260°C peak, 10 seconds maximum.
2,000 hours at +125°C, maximum bias, disregarding frequency shift.
1,000 hours at +85°C, full bias, less than ±5 ppm shift.
Level 1 per JEDEC J-STD-020.
QUALITY AND RELIABILITY
Quality systems meet or exceed the requirements of ISO 9000:2000 standards.
Document No. 008-0316-0
Page 5 - 5
Rev. A
٠ ٠ ٠
CTS Electronic Components, Inc.
٠
171 Covington Drive
٠
Bloomingdale, IL 60108
٠٠٠
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