DATASHEET
LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER
Description
The ICS670-01 is a high-speed, low phase noise, Zero
Delay Buffer (ZDB) which integrates IDT’s proprietary
analog/digital Phase Locked Loop (PLL) techniques. The
zero delay feature means that the rising edge of the input
clock aligns with the rising edges of the outputs. There are
two identical outputs on the chip. FBCLK should be
connected to FBIN. Each output has its own output enable
pin.
The ICS670-01 is ideal for synchronizing outputs in a large
variety of systems, from personal computers to data
communications to video. By allowing off-chip feedback
paths, the ICS670-01 can eliminate the delay through other
devices. The 15 different on-chip multipliers work in a
variety of applications. Arbitrary multiplication factors
(including fractions) can be configured on the ICS527.
ICS670-01
Features
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Packaged in 16-pin SOIC
Pb (lead) free package, RoHS compliant
Clock inputs from 5 to 160 MHz (see page 2)
Patented PLL with low phase noise
Output clocks up to 160 MHz at 3.3 V
15 selectable on-chip multipliers
Power down mode available
Low phase noise: -124 dBc/Hz at 10 kHz
Output enable function tri-states outputs
Low jitter–15 ps one sigma
Full swing CMOS outputs with 25 mA drive capability at
TTL levels
Advanced, low power, sub-micron CMOS process
Industrial temperature version available
Operating voltage of 3.3 V or 5 V
Block Diagram
VDD
3
OE1
ICLK
FBIN
Phase
Detector,
Charge
Pump, and
Loop Filter
Voltage
Controlled
Oscillator
ROM-
Based
Multipliers
FBCLK
S3:S0
4
CLK2
3
GND
External Feedback from FBCLK is recommended.
OE2
IDT®
LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER
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ICS670-01
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ICS670-01
LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER
ZDB AND MULTIPLIER
Pin Assignment
VDD
VDD
VDD
CLK2
OE2
FBCLK
OE1
FBIN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
GND
GND
S0
S1
S2
S3
ICLK
Multiplier Select Table
S3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
S2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CLK2 (and FBCLK)
Low (Power down entire
chip)
Input x1.333
Input x6
Input x1.5
Input x3.333
Input x2.50
Input x4
Input x1
Input x2.333
Input x2.666
Input x12
Input x3
Input x10
Input x5
Input x8
Input x2
Input Range (MHz)
-
18 - 120
5 - 26.67
16.67 - 107
7.5 - 48
10 - 64
6 - 40
25 - 160
11 - 69
10 - 60
5 - 13.33
8 - 53.33
5 - 16
6 - 32
5 - 20
12 - 80
Pin Descriptions
Pin
Number
1-3
4
5
6
7
8
9
10
11
12
13
14 - 16
Pin
Name
VDD
CLK2
OE2
FBCLK
OE1
FBIN
ICLK
S3
S2
S1
S0
GND
Pin
Type
Input
Pin Description
Power supply. Connect all pins to the same voltage (either 3.3 V or 5 V). Pins
1 and 2 supply the analog sections of the chip.
Output Clock output from VCO. Output frequency equals the input frequency times
multiplier.
Input
Output clock enable 2. Tri-states the clock 2 output when low.
Output Clock output from VCO. Output frequency equals the input frequency times
multiplier.
Input
Input
Input
Input
Input
Input
Input
Power
Output clock enable 1. Tri-states the feedback clock output when low.
Feedback clock input.
Clock input. Connect to a 5 - 210 MHz clock.
Multiplier select pin 3. Determines outputs per table above. Internal pull-up.
Multiplier select pin 2. Determines outputs per table above. Internal pull-up.
Multiplier select pin 1. Determines outputs per table above. Internal pull-up.
Multiplier select pin 0. Determines outputs per table above. Internal pull-up.
Connect to ground.
IDT®
LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER
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LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER
ZDB AND MULTIPLIER
External Components
The ICS670-01 requires a minimum number of external components for proper operation. Decoupling capacitors of
0.01µF should be connected from each VDD pin to the ground plane, as close to the device as possible. A series
termination resistor of 33 should be used to each clock output pin.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS670-01. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Ambient Operating Temperature, ICS670-01I
Storage Temperature
Junction Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
0 to +70C
-40 to +85C
-65 to +150C
125C
260C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
0
+3.0
Typ.
Max.
+70
+5.5
Units
C
V
DC Electrical Characteristics
VDD=3.3V ±10%,
Ambient temperature -40 to +85C, unless stated otherwise
Parameter
Operating Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage,
CMOS level
Operating Supply Current
Short Circuit Current
Internal Pull-up Resistor
Input Capacitance
Symbol
VDD
V
IH
V
IL
V
OH
V
OL
V
OH
IDD
I
OS
R
PU
C
IN
Conditions
Min.
3.0
2
Typ.
Max.
5.5
0.8
Units
V
V
V
V
V
V
I
OH
= -12 mA
I
OL
= 12 mA
I
OH
= -4 mA
No Load
Each output
OE, select pins
OE, select pins
2.4
0.4
VDD-0.4
35
±50
200
5
mA
mA
k
pF
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LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER
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LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER
ZDB AND MULTIPLIER
AC Electrical Characteristics
VDD = 3.3V ±10%,
Ambient Temperature -40 to +85C, unless stated otherwise
Parameter
Input Clock Frequency
Output Clock Frequency
PLL Stabilization Time
Output Rise Time
Output Fall Time
Output Clock Duty Cycle
Input to Output Skew
Maximum Absolute Jitter
Maximum Jitter
Phase Noise, relative to
carrier, 125 MHz (x5)
Symbol
f
IN
t
STAB
t
OR
t
OF
t
DC
Conditions
See table on page 2
Input frequency 5 MHz to 160 MHz
0.8 to 2.0 V, no load
2.0 to 0.8 V, no load
measured at VDD/2
Note 1
short term
one sigma
100 Hz offset
1 kHz offset
10 kHz
200 kHz
Min.
5
Typ.
Max. Units
160
160
MHz
MHz
µs
ns
ns
%
ps
ps
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
4
10
1.5
1.5
45
50
±100
±45
15
-110
-122
-124
-117
55
Note 1: Rising edge of ICLK compared with rising edge of CLK2, with FBCLK connected to FBIN, and
15 pF load on CLK2. See graph on page 5 for skew vs. frequency and loading.
Thermal Characteristics
Parameter
Thermal Resistance Junction to
Ambient
Symbol
JA
JA
JA
JC
Conditions
Still air
1 m/s air flow
3 m/s air flow
Min.
Typ.
120
115
105
58
Max. Units
C/W
C/W
C/W
C/W
Thermal Resistance Junction to Case
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LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER
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LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER
ZDB AND MULTIPLIER
Figure 1. Skew from ICLK to CLK2
, with change in load capacitance (VDD = 3.3V)
300
200
100
Skew (ps)
0
-100
-200
-300
-400
CLK2 Frequency (MHz)
Skew (ps) 20 pF
Skew (ps) 10 pF
25
50
75
100
125
150
Adjusting Input/Output Skew
The data in Figure 1 can be used to adjust individual circuit characteristics and achieve the minimum possible skew
between ICLK and CLK2. With a 125 MHz output, for example, having a total load capacitance of 15 pF will result
in nearly zero skew between ICLK and CLK2. Note that the load
capacitance includes board trace capacitance, input capacitance of the load being driven by the ICS670-01, and
any additional capacitors connected to CLK2.
Figure 2. Phase Noise for 125 MHz output, 25 MHz clock input
(VDD = 3.3V)
ICS670 Phase noise
0
-20
-40
-60
L(f) dBc
-80
-100
-120
-140
10.E+0
100.E+0
1.E+3
10.E+3
offset frequency
100.E+3
1.E+6
10.E+6
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LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER
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