HC05CL48GRS/H
REV 2.0
68HC05CL48
68HC705CL48
68HC05CL16
68HC705CL16
SPECIFICATION
(General Release)
© June 11, 1997
Hong Kong Design Center
CSIC Group
Motorola reserves the right to make changes without further notice to any products herein
to improve reliability, function or design. Motorola does not assume any liability arising out
of the application or use of any product or circuit described herein; neither does it convey
any license under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or other applications intended to support or sustain life, or for any
other application in which the failure of the Motorola product could create a situation
where personal injury or death may occur. Should Buyer purchase or use Motorola
products for any such unintended or unauthorized application, Buyer shall indemnify and
hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable attorney
fees arising out of, directly or indirectly, any claim of personal injury or death associated
with such unintended or unauthorized use, even if such claim alleges that Motorola was
negligent regarding the design or manufacture of the part.
©
Motorola, Inc., 1997
June 11, 1997
GENERAL RELEASE SPECIFICATION
TABLE OF CONTENTS
Section
SECTION 1
GENERAL DESCRIPTION
1.1
FEATURES ...................................................................................................... 1-1
1.2
MCU STRUCTURE.......................................................................................... 1-3
1.3
PIN ASSIGNMENT .......................................................................................... 1-4
1.4
SIGNAL DESCRIPTION .................................................................................. 1-5
1.4.1
V
DD
and V
SS
................................................................................................ 1-5
1.4.2
RESET......................................................................................................... 1-5
1.4.3
IRQ .............................................................................................................. 1-5
1.4.4
IRQ0, IRQ1, IRQ2........................................................................................ 1-6
1.4.5
OSC1, OSC2 ............................................................................................... 1-6
1.4.6
External Clock.............................................................................................. 1-7
1.4.7
PTA0-PTA7.................................................................................................. 1-7
1.4.8
PTB0-PTB7.................................................................................................. 1-7
1.4.9
PTC0-PTC7 ................................................................................................. 1-7
1.4.10 SCK ............................................................................................................. 1-8
1.4.11 MISO, MOSI ................................................................................................ 1-8
1.4.12 SS ................................................................................................................ 1-8
1.4.13 AD0-AD3...................................................................................................... 1-8
1.4.14 TCAP1 ......................................................................................................... 1-8
1.4.15 TCAP2 ......................................................................................................... 1-8
1.4.16 FSK+, FSK–................................................................................................. 1-8
1.4.17 RT_L ............................................................................................................ 1-9
1.4.18 RD1, RD2 .................................................................................................... 1-9
1.4.19 BP0 - BP15 .................................................................................................. 1-9
1.4.20 FP0 - FP44 .................................................................................................. 1-9
1.4.21 VLCD, V0, V1, V2, V3, V4 ........................................................................... 1-9
1.4.22 XFC.............................................................................................................. 1-9
SECTION 2
MEMORY
2.1
2.2
2.2.1
2.3
2.4
2.5
2.6
MEMORY MAP ................................................................................................ 2-1
I/O AND CONTROL REGISTERS ................................................................... 2-1
Option Register ($1F) .................................................................................. 2-1
LCD RAM ......................................................................................................... 2-2
RAM ................................................................................................................. 2-2
ROM................................................................................................................. 2-2
I/O MAPPED REGISTERS .............................................................................. 2-2
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MC68HC05CL48
REV 2.0
MOTOROLA
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GENERAL RELEASE SPECIFICATION
June 11, 1997
TABLE OF CONTENTS
Section
SECTION 3
CPU
3.1
REGISTERS .................................................................................................... 3-1
3.1.1
Accumulator (A) ........................................................................................... 3-1
3.1.2
Index Register (X)........................................................................................ 3-2
3.1.3
Stack Pointer (SP) ....................................................................................... 3-2
3.1.4
Program Counter (PC)................................................................................. 3-2
3.1.5
Condition Code Register (CCR) .................................................................. 3-3
SECTION 4
INTERRUPTS
4.1
RESET INTERRUPT SEQUENCE .................................................................. 4-3
4.2
SOFTWARE INTERRUPT (SWI) ..................................................................... 4-3
4.3
HARDWARE INTERRUPTS ............................................................................ 4-3
4.3.1
External Interrupt (IRQ) ............................................................................... 4-3
4.3.2
External Interrupts (IRQ0, IRQ1, IRQ2, KBI[3:7]) ........................................ 4-6
4.3.3
Caller ID Interrupt (RDI/CDI,CDRI).............................................................. 4-8
4.3.4
TIMER Interrupt ........................................................................................... 4-8
4.3.5
SPI Interrupt................................................................................................. 4-9
4.3.6
CTIMER, WTimer Interrupt (CORE TIMER, Watch Timer).......................... 4-9
SECTION 5
RESETS
5.1
5.2
5.3
EXTERNAL RESET (RESET).......................................................................... 5-1
POWER-ON RESET (POR)............................................................................. 5-1
COMPUTER OPERATING PROPERLY RESET (COPR) ............................... 5-2
SECTION 6
LOW POWER MODES
6.1
LOW-POWER MODES .................................................................................... 6-1
6.1.1
STOP Instruction ......................................................................................... 6-1
6.1.2
WAIT Instruction .......................................................................................... 6-1
6.2
DATA-RETENTION MODE.............................................................................. 6-2
6.3
COP WATCHDOG TIMER CONSIDERATIONS ............................................. 6-2
SECTION 7
INPUT/OUTPUT PORTS
7.1
7.2
7.3
7.4
PARALLEL PORTS.......................................................................................... 7-1
PORT A............................................................................................................ 7-2
PORT B............................................................................................................ 7-2
PORT C............................................................................................................ 7-2
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MOTOROLA
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MC68HC05CL48
REV 2.0
June 11, 1997
GENERAL RELEASE SPECIFICATION
TABLE OF CONTENTS
Section
SECTION 8
TIMER
8.1
16-BIT FREE-RUNNING TIMER...................................................................... 8-1
8.1.1
Counter ........................................................................................................ 8-3
8.1.2
Output Compare Registers .......................................................................... 8-5
8.1.3
Input Capture Registers............................................................................... 8-8
8.1.4
Timer Control Register (TCR).................................................................... 8-11
8.1.5
Timer Status Register (TSR) ..................................................................... 8-12
8.1.6
Timer Pin Configuration Register (TIMCONF)........................................... 8-14
8.1.7
Operation During Low Power Mode........................................................... 8-14
8.2
CORE TIMER................................................................................................. 8-14
8.2.1
Computer Operating Properly (COP) Watchdog reset .............................. 8-16
8.2.2
Ctimer Control and Status Register (CTCSR) ........................................... 8-16
8.2.3
Ctimer Counter Register (CTCR)............................................................... 8-17
8.2.4
Operation During Low Power Mode........................................................... 8-18
8.3
ONE SECOND WATCH TIMER..................................................................... 8-19
8.3.1
Watch Timer Control & Status Register (WTCSR) .................................... 8-20
SECTION 9
SERIAL PERIPHERAL INTERFACE
9.1
SIGNAL DESCRIPTION .................................................................................. 9-1
9.1.1
MISO Master In Slave Out........................................................................... 9-1
9.1.2
MOSI Serial Data In (Input) ......................................................................... 9-2
9.1.3
SCK Serial Clock (In/Out) ............................................................................ 9-2
9.1.4
SS SLAVE SELECT (INPUT) ...................................................................... 9-3
9.2
SPI REGISTERS.............................................................................................. 9-3
9.2.1
SPCR SPI Control Register ......................................................................... 9-4
9.2.2
SPSR SPI Status Register........................................................................... 9-6
9.2.3
SPDR SPI Data Register ............................................................................. 9-6
SECTION 10
ANALOG TO DIGITAL CONVERTER
10.1 ANALOG SECTION ....................................................................................... 10-1
10.1.1 Ratiometric Conversion ............................................................................. 10-1
10.1.2 V
RH
and V
RL ........................................................................................................................ 10-1
10.1.3 Accuracy And Precision............................................................................. 10-1
10.2 CONVERSION PROCESS ............................................................................ 10-1
10.3 DIGITAL SECTION ........................................................................................ 10-2
10.3.1 Conversion Time........................................................................................ 10-2
10.3.2 Multi-Channel Operation............................................................................ 10-2
10.4 A/D STATUS AND CONTROL REGISTER (ADCSR) ................................... 10-2
10.4.1 COCO - Conversions Complete ................................................................ 10-2
MC68HC05CL48
REV 2.0
MOTOROLA
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