Freescale Semiconductor, Inc.
Addendum
HC908LJ12AD/D
Rev. 0, 6/2003
Addendum to
MC68HC908LJ12
Technical Data
Freescale Semiconductor, Inc...
This addendum provides information to the following MCU devices:
•
•
MC68HLC908LJ12
(see
page 1)
MC68HC08LJ12
(see
page 9)
The entire
MC68HC908LJ12 Technical Data,
Rev. 2 (Motorola document
number MC68HC908LJ12/D) applies to the these two devices, with exceptions
outlined in this addendum.
Amendments to
MC68HC908LJ12/D,
Rev. 2, are documented on
page 13.
MC68HLC908LJ12
The MC68HLC908LJ12 is a low-voltage version of the MC68HC908LJ12, with
an operating voltage range of 2.4 to 3.3V.
FLASH Memory
The FLASH memory can be read at operating voltages from 2.4 to 3.3V.
Program or erase operations require a minimum operating voltage of 2.7V.
Low-Voltage Inhibit
(LVI)
The LVI module is not designed for the MC68HLC908LJ12. After an MCU
reset, the LVI module is disabled (LVIPWRD = 1 in CONFIG1). The LVIPWRD
bit should be left as logic 1 (the default setting).
Electrical
Specifications
Electrical specifications for the MC68HLC908LJ12 device are given in the
following tables.
© Motorola, Inc., 2003
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HC908LJ12AD/D
Functional Operating
Range
Table 1. Operating Range
Characteristic
Operating temperature range
Operating voltage range
Maximum internal operating
frequency
Symbol
T
A
V
DD
f
OP
Value
– 40 to +85
2.4 to 2.7
2
2.7 to 3.3
4
Unit
°
C
V
MHz
Freescale Semiconductor, Inc...
Operating voltage for FLASH
memory program and erase
operations
V
DD
2.7 to 3.3
V
DC Electrical
Characteristics
Table 2. DC Electrical Characteristics (2.4 to 2.7V)
Characteristic
(1)
Output high voltage (I
LOAD
= –1.0 mA)
All ports
Output low voltage
(I
LOAD
= 0.8mA) All ports
(I
LOAD
= 4.0 mA) PTB2–PTB5
(I
LOAD
= 10.0 mA) PTB0/TxD–PTB1
Input high voltage
All ports, RST, IRQ, OSC1
Input low voltage
All ports, RST, IRQ, OSC1
V
DD
supply current
Run
(3)
, f
OP
= 2 MHz
with all modules on
with ADC on
with ADC off
Wait
(4)
, f
OP
= 2 MHz (all modules off)
Stop, f
OP
= 8 kHz
(5)
25
°
C (with OSC, RTC, LCD
(6)
, LVI on)
25
°
C (with OSC, RTC, LCD
(6)
on)
25
°
C (with OSC, RTC on)
25
°
C (all modules off)
Digital I/O ports Hi-Z leakage current
All ports, RST
I
IL
—
—
—
—
—
—
—
—
—
—
200
27
15
1
—
—
—
—
—
—
—
—
5.2
3.8
2.8
2.3
mA
mA
mA
mA
Symbol
V
OH
Min
V
DD
–0.4
Typ
(2)
—
Max
—
Unit
V
V
OL
—
—
0.4
V
V
IH
V
IL
0.7
×
V
DD
V
SS
—
—
V
DD
0.3
×
V
DD
V
V
I
DD
µ
A
µ
A
µ
A
µ
A
µ
A
±
10
2
Addendum to MC68HC908LJ12 Technical Data
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HC908LJ12AD/D
MC68HLC908LJ12
Table 2. DC Electrical Characteristics (2.4 to 2.7V) (Continued)
Characteristic
(1)
Input current
IRQ
Capacitance
Ports (as input or output)
POR re-arm voltage
(7)
POR rise-time ramp rate
(8)
Symbol
I
IN
C
OUT
C
IN
V
POR
R
POR
V
HI
R
PU1
R
PU2
Min
—
—
—
0
0.02
1.5
×
V
DD
—
—
Typ
(2)
—
—
—
—
—
—
25
27
Max
Unit
±
1
12
8
100
—
2
×
V
DD
—
—
µ
A
pF
mV
V/ms
V
k
Ω
k
Ω
Freescale Semiconductor, Inc...
Monitor mode entry voltage (at IRQ pin)
Pullup resistors
(9)
PTA0–PTA3, PTD4–PTD7 configured as KBI0–KBI7
RST, IRQ
1. V
DD
= 2.4 to 2.7 Vdc, V
SS
= 0 Vdc, T
A
= T
L
to T
H
, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25
°C
only.
3. Run (operating) I
DD
measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than
100 pF on all outputs. C
L
= 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run I
DD
.
4. Wait I
DD
measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than 100 pF on
all outputs. C
L
= 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait I
DD
.
5. The 8kHz clock is from a 32kHz clock input at OSC1, for the driving the RTC.
6. LCD driver configured for low current mode.
7. Maximum is highest voltage that POR is guaranteed.
8. If minimum V
DD
is not reached before the internal POR reset is released,
RST
must be driven low externally until minimum
V
DD
is reached.
9. R
PU1
and R
PU2
are measured at V
DD
= 2.6V.
Table 3. DC Electrical Characteristics (2.7 to 3.3V)
Characteristic
(1)
Output high voltage (I
LOAD
= –1.0 mA)
All ports
Output low voltage
(I
LOAD
= 0.8mA) All ports
(I
LOAD
= 4.0 mA) PTB2–PTB5
(I
LOAD
= 10.0 mA) PTB0/TxD–PTB1
Input high voltage
All ports, RST, IRQ, OSC1
Input low voltage
All ports, RST, IRQ, OSC1
Symbol
V
OH
Min
V
DD
–0.4
Typ
(2)
—
Max
—
Unit
V
V
OL
—
—
0.4
V
V
IH
V
IL
0.7
×
V
DD
V
SS
—
—
V
DD
0.3
×
V
DD
V
V
MOTOROLA
Addendum to MC68HC908LJ12 Technical Data
3
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HC908LJ12AD/D
Table 3. DC Electrical Characteristics (2.7 to 3.3V) (Continued)
Characteristic
(1)
V
DD
supply current
Run
(3)
, f
OP
= 4 MHz
with all modules on
with ADC on
with ADC off
Wait
(4)
, f
OP
= 4 MHz (all modules off)
Stop, f
OP
= 8 kHz
(5)
25
°
C (with OSC, RTC, LCD
(6)
, LVI on)
25
°
C (with OSC, RTC, LCD
(6)
on)
25
°
C (with OSC, RTC on)
25
°
C (all modules off)
Digital I/O ports Hi-Z leakage current
All ports, RST
Input current
IRQ
Capacitance
Ports (as input or output)
POR re-arm voltage
(7)
POR rise-time ramp rate
(8)
Monitor mode entry voltage (at IRQ pin)
Pullup resistors
(9)
PTA0–PTA3, PTD4–PTD7 configured as KBI0–KBI7
RST, IRQ
I
IL
I
IN
C
OUT
C
IN
V
POR
R
POR
V
HI
R
PU1
R
PU2
—
—
—
—
—
—
—
—
—
—
—
—
0
0.02
1.5
×
V
DD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
25
27
8
6
5
3.5
280
38
15
1
mA
mA
mA
mA
Symbol
Min
Typ
(2)
Max
Unit
I
DD
Freescale Semiconductor, Inc...
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
pF
mV
V/ms
V
k
Ω
k
Ω
±
10
±
1
12
8
100
—
2
×
V
DD
—
—
1. V
DD
= 2.7 to 3.3 Vdc, V
SS
= 0 Vdc, T
A
= T
L
to T
H
, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25
°C
only.
3. Run (operating) I
DD
measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than
100 pF on all outputs. C
L
= 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run I
DD
.
4. Wait I
DD
measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than 100 pF on
all outputs. C
L
= 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait I
DD
.
5. The 8kHz clock is from a 32kHz clock input at OSC1, for the driving the RTC.
6. LCD driver configured for low current mode.
7. Maximum is highest voltage that POR is guaranteed.
8. If minimum V
DD
is not reached before the internal POR reset is released,
RST
must be driven low externally until minimum
V
DD
is reached.
9. R
PU1
and R
PU2
are measured at V
DD
= 3V.
4
Addendum to MC68HC908LJ12 Technical Data
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HC908LJ12AD/D
MC68HLC908LJ12
Oscillator
Characteristics
Table 4. Oscillator Specifications (2.4 to 2.7V)
Characteristic
Internal oscillator clock frequency
External reference clock to OSC1
(1)
Crystal reference frequency
(2)
Crystal load capacitance
(3)
Symbol
f
ICLK
f
OSC
f
XCLK
C
L
C
1
C
2
R
B
R
S
—
—
—
—
—
Min
—
dc
Typ
See
Figure 1.
—
32.768k
—
2
×
C
L
(25p)
2
×
C
L
(25p)
10M
100k
Max
—
8M
4.9152M
—
—
—
—
—
F
F
Unit
Hz
Hz
Hz
Freescale Semiconductor, Inc...
Crystal fixed capacitance
Crystal tuning capacitance
Feedback bias resistor
Series resistor
(4)
1. No more than 10% duty cycle deviation from 50%.
2. Fundamental mode crystals only.
3. Consult crystal manufacturer’s data.
4. Not Required for high frequency crystals.
Ω
Ω
Table 5. Oscillator Specifications (2.7 to 3.3V)
Characteristic
Internal oscillator clock frequency
External reference clock to OSC1
(1)
Crystal reference frequency
(2)
Crystal load capacitance
(3)
Crystal fixed capacitance
Crystal tuning capacitance
Feedback bias resistor
Series resistor
(4)
1. No more than 10% duty cycle deviation from 50%.
2. Fundamental mode crystals only.
3. Consult crystal manufacturer’s data.
4. Not Required for high frequency crystals.
Symbol
f
ICLK
f
OSC
f
XCLK
C
L
C
1
C
2
R
B
R
S
Min
—
dc
Typ
See
Figure 1.
—
32.768k
Max
—
16M
4.9152M
—
—
—
—
—
Unit
Hz
Hz
Hz
—
—
—
—
—
—
2
×
C
L
(25p)
2
×
C
L
(25p)
10M
100k
F
F
Ω
Ω
MOTOROLA
Addendum to MC68HC908LJ12 Technical Data
5
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