型号
  • 型号
  • 关键词
首页 > 器件类别 > 存储 > 存储

70125S55J

SRAM 2KX9 DUAL PORT SLAVE W/IN

器件类别：存储    存储   

厂商名称：IDT (Integrated Device Technology)

下载文档
参数 预览 参数对比
70125S55J 在线购买

供应商：

器件：70125S55J

价格：-

最低购买：-

库存：点击查看

点击购买

器件参数
参数名称
属性值
Brand Name
Integrated Device Technology
是否无铅
含铅
是否Rohs认证
不符合
零件包装代码
PLCC
包装说明
0.750 X 0.750 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-52
针数
52
制造商包装代码
PL52
Reach Compliance Code
not_compliant
ECCN代码
EAR99
最长访问时间
55 ns
I/O 类型
COMMON
JESD-30 代码
S-PQCC-J52
JESD-609代码
e0
长度
19.1262 mm
内存密度
18432 bit
内存集成电路类型
DUAL-PORT SRAM
内存宽度
9
湿度敏感等级
3
功能数量
1
端口数量
2
端子数量
52
字数
2048 words
字数代码
2000
工作模式
ASYNCHRONOUS
最高工作温度
70 °C
最低工作温度
组织
2KX9
输出特性
3-STATE
封装主体材料
PLASTIC/EPOXY
封装代码
QCCJ
封装等效代码
LDCC52,.8SQ
封装形状
SQUARE
封装形式
CHIP CARRIER
并行/串行
PARALLEL
峰值回流温度（摄氏度）
225
电源
5 V
认证状态
Not Qualified
座面最大高度
4.57 mm
最大待机电流
0.015 A
最小待机电流
2 V
最大压摆率
0.24 mA
最大供电电压 (Vsup)
5.5 V
最小供电电压 (Vsup)
4.5 V
标称供电电压 (Vsup)
5 V
表面贴装
YES
技术
CMOS
温度等级
COMMERCIAL
端子面层
Tin/Lead (Sn85Pb15)
端子形式
J BEND
端子节距
1.27 mm
端子位置
QUAD
处于峰值回流温度下的最长时间
NOT SPECIFIED
宽度
19.1262 mm
Base Number Matches
1
文档预览
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
HIGH-SPEED
2K x 9 DUAL-PORT
STATIC RAM
WITH BUSY & INTERRUPT
◆
◆
IDT70121S/L
IDT70125S/L
Features
✵
◆
High-speed access
– Commercial: 25/35/55ns (max.)
– Industrial: 35ns (max.)
Low-power operation
– IDT70121/70125S
Active: 675mW (typ.)
Standby: 5mW (typ.)
– IDT70121/70125L
Active: 675mW (typ.)
Standby: 1mW (typ.)
◆
◆
◆
◆
◆
◆
◆
◆
Fully asychronous operation from either port
MASTER IDT70121 easily expands data bus width to 18 bits or
more using SLAVE IDT70125 chip
On-chip port arbitration logic (IDT70121 only)
BUSY
output flag on Master;
BUSY
input on Slave
INT
flag for port-to-port communication
Battery backup operation—2V data retention
TTL-compatible, signal 5V (±10%) power supply
Available in 52-pin PLCC
Industrial temperature range (–40°C to +85°C) is available for
selected speeds
Green parts available, see ordering information
Functional Block Diagram
OE
L
CE
L
R/W
L
OE
R
CE
R
R/W
R
I/O
0L
- I/O
8L
I/O
Control
BUSY
L
A
10L
A
0L
(1,2)
I/O
0R
-I/O
8R
I/O
Control
BUSY
R
Address
Decoder
11
(1,2)
MEMORY
ARRAY
11
Address
Decoder
A
10R
A
0R
CE
L
OE
L
R/W
L
ARBITRATION
INTERRUPT
LOGIC
CE
R
OE
R
R/W
R
INT
L
(2)
INT
R
2654 drw 01
(2)
NOTES:
1. 70121 (MASTER):
BUSY
is non-tri-stated push-pull output.
70125 (SLAVE):
BUSY
is input.
2.
INT
is non-tri-stated push-pull output.
OCTOBER 2017
1
©2017 Integrated Device Technology, Inc.
DSC 2654/14
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt
Industrial and Commercial Temperature Ranges
Description
The IDT70121/IDT70125 are high-speed 2K x 9 Dual-Port Static
RAMs. The IDT70121 is designed to be used as a stand-alone 9-bit Dual-
Port RAM or as a “MASTER” Dual-Port RAM together with the IDT70125
“SLAVE” Dual-Port in 18-bit-or-more word width systems. Using the IDT
MASTER/SLAVE Dual-Port RAM approach in 18-bit-or-wider memory
system applications results in full-speed, error-free operation without the
need for additional discrete logic.
Both devices provide two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power-down
feature, controlled by
CE,
permits the on-chip circuitry of each port to enter
a very low standby power mode.
The IDT70121/IDT70125 utilizes a 9-bit wide data path to allow for
Data/Control and parity bits at the user’s option. This feature is especially
useful in data communications applications where it is necessary to use a
parity bit for transmission/reception error checking.
Fabricated using CMOS high-performance technology, these
devices typically operate on only 675mW of power. Low-power (L)
versions offer battery backup data retention capability with each port
typically consuming 200µW from a 2V battery.
The IDT70121/IDT70125 devices are packaged in a 52-pin PLCC.
03/05/18
Pin Configurations
(1,2,3)
A
0L
OE
L
A
10L
INT
L
BUSY
L
R/W
L
CE
L
V
CC
CE
R
R/W
R
BUSY
R
INT
R
A
10R
51
50
7
6
5
52
48
47
49
3
4
2
21
22
23
24
25
26
27
28
30
31
INDEX
I/O
4L
I/O
5L
I/O
6L
I/O
7L
I/O
8L
GND
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
I/O
6R
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately .75 in x .75 in x .17 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
32
29
33
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
I/O
3L
8
9
10
11
12
13
14
15
16
17
18
19
20
46
45
44
43
IDT70121/125J
J52
(4)
52-Pin PLCC
Top View
(5)
42
41
40
39
38
37
36
35
34
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
I/O
8R
I/O
7R
2654 drw 02
2
6.42
1
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt
Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
Rating
Terminal Voltage
with Respect
to GND
Temperature
Under Bias
Storage
Temperature
DC Output
Current
Commercial
& Industrial
-0.5 to +7.0
Unit
V
Recommended DC
Operating Conditions
Symbol
V
CC
GND
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
-0.5
(1)
Typ.
5.0
0
____
____
Max.
5.5
0
6.0
(2)
0.8
Unit
V
V
V
V
2654 tbl 03
T
BIAS
T
STG
I
OUT
-55 to +125
-65 to +150
50
o
C
C
V
IH
V
IL
o
mA
2654 tbl 01
NOTES:
1. V
IL
> -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed Vcc + 10%.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
TERM
must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> V
cc
+ 10%.
Capacitance
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
(1)
V
IN
= 3dV
V
OUT
= 3dV
Max.
9
10
Unit
pF
pF
2654 tbl 04
Maximum Operating Temperature
and Supply Voltage
(1)
Grade
Commercial
Industrial
Ambient
Temperature
0
O
C to +70
O
C
-40
O
C to +85
O
C
GND
0V
0V
Vcc
5.0V
+
10%
5.0V
+
10%
2654 tbl 02
NOTE:
1. This parameter is determined by device characterization but is not production
tested.
NOTES:
1. This is the parameter T
A
. This is the "instant on" case temperature.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(V
CC
= 5.0V ± 10%)
70121S
70125S
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
(1)
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Conditions
V
CC
= 5.5V, V
IN
= 0V to V
CC
V
CC
= 5.5V,
CE
= V
IH
, V
OUT
= 0V to V
CC
I
OL
= +4mA
I
OH
= -4mA
Min.
___
___
___
70121L
70125L
Max.
10
10
0.4
___
Min.
___
___
___
Max.
5
5
0.4
___
Unit
µA
µA
V
V
2654 tbl 05
2.4
2.4
NOTE:
1. At Vcc < 2.0V leakages are undefined.
3
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(1,4)
(V
CC
= 5V ± 10%)
70121X25
70125X25
Com'l Only
Symbol
I
CC
Parameter
Dynamic Operating Current
(Both Ports Active)
Test Condition
CE
= V
IL
, Outputs Disabled
f = f
MAX
(2)
Version
COM'L
IND
COM'L
IND
COM'L
IND
COM'L
IND
COM'L
IND
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
Typ.
135
135
___
___
70121X35
70125X35
Com'l
& Ind
Typ.
135
135
135
135
30
30
30
30
80
80
80
80
1.0
0.2
1.0
0.2
70
70
70
70
Max.
250
210
275
250
65
45
80
65
165
135
190
165
15
5
15
5
160
130
185
160
2654 tbl 06a
Max.
260
220
___
___
Unit
mA
I
SB1
Standby Current
(Both Ports - TTL Level Inputs)
CE
"A"
=
CE
"B"
= V
IH
f = f
MAX
(2)
30
30
___
___
65
45
___
___
mA
I
SB2
Standby Current
(One Port - TTL Level Inputs)
CE
"A"
= V
IL
and
CE
"B"
= V
IH
(5)
Active Port Outputs Disabled,
f=f
MAX
(2)
80
80
___
___
175
145
___
___
mA
I
SB3
Full Standby Current (Both Ports
- CMOS Level Inputs)
CE
"A"
and
CE
"B"
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or
VIN < 0.2V, f = 0
(3)
1.0
0.2
___
___
15
5
___
___
mA
I
SB4
Full Standby Current
(One Port - CMOS Level Inputs)
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(5)
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Active Port Outputs Disabled,
f = f
MAX
(2)
70
70
___
___
170
140
___
___
mA
70121X55
70125X55
Com'l Only
Symbol
I
CC
Parameter
Dynamic Operating Current
(Both Ports Active)
Test Condition
CE
= V
IL
, Outputs Disabled
f = f
MAX
(2)
Version
COM'L
IND
COM'L
IND
COM'L
IND
COM'L
IND
COM'L
IND
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
Typ.
135
135
___
___
Max.
240
200
___
___
Unit
mA
I
SB1
Standby Current
(Both Ports - TTL Level Inputs)
CE
"A"
=
CE
"B"
= V
IH
f = f
MAX
(2)
30
30
___
___
65
45
___
___
mA
I
SB2
Standby Current
(One Port - TTL Level Inputs)
CE
"A"
= V
IL
and
CE
"B"
= V
IH
(5)
Active Port Outputs Disabled,
f=f
MAX
(2)
80
80
___
___
155
125
___
___
mA
I
SB3
Full Standby Current
(Both Ports - CMOS Level
Inputs)
CE
"A"
and
CE
"B"
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(3)
1.0
0.2
___
___
15
5
___
___
mA
I
SB4
Full Standby Current
(One Port - CMOS Level Inputs)
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(5)
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Active Port Outputs Disabled,
f = f
MAX
(2)
70
70
___
___
150
120
___
___
mA
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
2. At f = f
MAX
, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/t
RC
, and using “AC TEST CONDITIONS” of
input levels of GND to 3V.
3. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
4. Vcc=5V, T
A
=+25°C for Typ, and is not production tested.
5. Port "A" may be either left or right port. Port "B" is opposite from port "A".
2654 tbl 06b
4
6.42
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt
Industrial and Commercial Temperature Ranges
Data Retention Characteristics
(L Version Only)
Symbol
V
DR
I
CCDR
t
CDR
(3)
t
R
(3)
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
V
CC
= 2V,
CE
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or V
IN
< 0.2
IND.
COM'L.
Test Condition
Min.
2.0
___
___
Typ.
(1)
___
Max.
___
Unit
V
µA
100
100
___
4000
1500
___
t
RC
(2)
V
2654 tbl 07
NOTES:
1. V
CC
= 2V, T
A
= +25°C, and are not production tested.
2. t
RC
= Read Cycle Time.
3. This parameter is guaranteed but is not production tested.
Data Retention Waveform
DATA RETENTION MODE
Vcc
4.5V
t
CDR
CE
V
IH
V
DR
V
DR
≥
2V
4.5V
t
R
V
IH
2654 drw 03
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
Figures 1 and 2
2654 tbl 08
5V
1250Ω
DATA
OUT
BUSY
INT
DATA
OUT
775Ω
30pF
775Ω
5V
1250Ω
5pF*
2654 drw 04
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(For t
LZ
, t
HZ
, t
WZ
, t
OW
)
*Including scope and jig.
5
查看更多>
参数对比
与70125S55J相近的元器件有：70125S55J8、70121S55J、70121L35J、70125L25J、70125L55J8、70125S35J、70121S25J、70125S25J8。描述及对比如下：
型号 70125S55J 70125S55J8 70121S55J 70121L35J 70125L25J 70125L55J8 70125S35J 70121S25J 70125S25J8
描述 SRAM 2KX9 DUAL PORT SLAVE W/IN SRAM 2KX9 DUAL PORT SLAVE W/IN SRAM 2KX9 DUAL PORT MASTR W/IN SRAM 2KX9 DUAL PORT MASTR W/IN SRAM 2KX9 DUAL PORT SLAVE W/IN SRAM 2KX9 DUAL PORT SLAVE W/IN SRAM 2KX9 DUAL PORT SLAVE W/IN SRAM 2KX9 DUAL PORT MASTR W/IN SRAM 2KX9 DUAL PORT SLAVE W/IN
Brand Name Integrated Device Technology Integrated Device Technology Integrated Device Technology Integrated Device Technology Integrated Device Technology Integrated Device Technology Integrated Device Technology Integrated Device Technology Integrated Device Technology
是否无铅 含铅 含铅 含铅 含铅 含铅 含铅 含铅 含铅 含铅
是否Rohs认证 不符合 不符合 不符合 不符合 不符合 不符合 不符合 不符合 不符合
零件包装代码 PLCC PLCC PLCC PLCC PLCC PLCC PLCC PLCC PLCC
包装说明 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-52 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-52 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-52 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-52 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-52 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-52 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-52 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-52 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-52
针数 52 52 52 52 52 52 52 52 52
制造商包装代码 PL52 PL52 PL52 PL52 PL52 PL52 PL52 PL52 PL52
Reach Compliance Code not_compliant not_compliant not_compliant not_compliant not_compliant not_compliant not_compliant not_compliant not_compliant
ECCN代码 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99
最长访问时间 55 ns 55 ns 55 ns 35 ns 25 ns 55 ns 35 ns 25 ns 25 ns
I/O 类型 COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON
JESD-30 代码 S-PQCC-J52 S-PQCC-J52 S-PQCC-J52 S-PQCC-J52 S-PQCC-J52 S-PQCC-J52 S-PQCC-J52 S-PQCC-J52 S-PQCC-J52
JESD-609代码 e0 e0 e0 e0 e0 e0 e0 e0 e0
长度 19.1262 mm 19.1262 mm 19.1262 mm 19.1262 mm 19.1262 mm 19.1262 mm 19.1262 mm 19.1262 mm 19.1262 mm
内存密度 18432 bit 18432 bit 18432 bit 18432 bit 18432 bit 18432 bit 18432 bit 18432 bit 18432 bit
内存集成电路类型 DUAL-PORT SRAM DUAL-PORT SRAM DUAL-PORT SRAM DUAL-PORT SRAM DUAL-PORT SRAM DUAL-PORT SRAM DUAL-PORT SRAM DUAL-PORT SRAM DUAL-PORT SRAM
内存宽度 9 9 9 9 9 9 9 9 9
湿度敏感等级 3 3 3 3 3 3 3 3 3
功能数量 1 1 1 1 1 1 1 1 1
端口数量 2 2 2 2 2 2 2 2 2
端子数量 52 52 52 52 52 52 52 52 52
字数 2048 words 2048 words 2048 words 2048 words 2048 words 2048 words 2048 words 2048 words 2048 words
字数代码 2000 2000 2000 2000 2000 2000 2000 2000 2000
工作模式 ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS
最高工作温度 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C
组织 2KX9 2KX9 2KX9 2KX9 2KX9 2KX9 2KX9 2KX9 2KX9
输出特性 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 QCCJ QCCJ QCCJ QCCJ QCCJ QCCJ QCCJ QCCJ QCCJ
封装等效代码 LDCC52,.8SQ LDCC52,.8SQ LDCC52,.8SQ LDCC52,.8SQ LDCC52,.8SQ LDCC52,.8SQ LDCC52,.8SQ LDCC52,.8SQ LDCC52,.8SQ
封装形状 SQUARE SQUARE SQUARE SQUARE SQUARE SQUARE SQUARE SQUARE SQUARE
封装形式 CHIP CARRIER CHIP CARRIER CHIP CARRIER CHIP CARRIER CHIP CARRIER CHIP CARRIER CHIP CARRIER CHIP CARRIER CHIP CARRIER
并行/串行 PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL
峰值回流温度（摄氏度） 225 225 225 225 225 225 225 225 225
电源 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
座面最大高度 4.57 mm 4.57 mm 4.57 mm 4.57 mm 4.57 mm 4.57 mm 4.57 mm 4.57 mm 4.57 mm
最大待机电流 0.015 A 0.015 A 0.015 A 0.005 A 0.015 A 0.015 A 0.015 A 0.015 A 0.015 A
最小待机电流 2 V 2 V 2 V 2 V 2 V 2 V 2 V 2 V 2 V
最大压摆率 0.24 mA 0.24 mA 0.24 mA 0.21 mA 0.22 mA 0.2 mA 0.25 mA 0.26 mA 0.26 mA
最大供电电压 (Vsup) 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V
最小供电电压 (Vsup) 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V
标称供电电压 (Vsup) 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V
表面贴装 YES YES YES YES YES YES YES YES YES
技术 CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
温度等级 COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
端子面层 Tin/Lead (Sn85Pb15) Tin/Lead (Sn85Pb15) Tin/Lead (Sn85Pb15) Tin/Lead (Sn85Pb15) Tin/Lead (Sn85Pb15) Tin/Lead (Sn85Pb15) Tin/Lead (Sn85Pb15) Tin/Lead (Sn85Pb15) Tin/Lead (Sn85Pb15)
端子形式 J BEND J BEND J BEND J BEND J BEND J BEND J BEND J BEND J BEND
端子节距 1.27 mm 1.27 mm 1.27 mm 1.27 mm 1.27 mm 1.27 mm 1.27 mm 1.27 mm 1.27 mm
端子位置 QUAD QUAD QUAD QUAD QUAD QUAD QUAD QUAD QUAD
处于峰值回流温度下的最长时间 NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
宽度 19.1262 mm 19.1262 mm 19.1262 mm 19.1262 mm 19.1262 mm 19.1262 mm 19.1262 mm 19.1262 mm 19.1262 mm
Base Number Matches 1 1 1 1 - 1 1 - 1
厂商名称 - - IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology)
maylove问你关于VISHAY消费主题月的问题
4月份的时候 我转到一个一等奖，但是没有提示，不知道有没有生效 当时第一次参加这个活动，转...
眼大5子 分立器件
学模拟+《运算放大器噪声优化手册》读书笔记之三
本帖最后由 dontium 于 2015-1-23 11:11 编辑 第三章包括了两个详...
oyueyueniao 模拟与混合信号
如何选择一款合适的红外热像仪？
红外热像仪及其工作原理，被动接收被测目标发出的红外辐射（热量），并将这种热能转化为带有温度数据...
安泰测试设备 测试/测量
【花雕体验】13 搭建ESP32C3之PlatformIO IDE开发环境
Visual Studio Code是一个轻量级但功能强大的源代码编辑器，可以在桌面上运行，可用于...
eagler8 DIY/开源硬件专区
PMC4351在便携式2M误码测试仪中的应用
PMC4351在便携式2M误码测试仪中的应用 PMC4351在便携式2M误码测试仪中的应用 ...
feifei 测试/测量
测判三极管的方法
大家知道，三极管是含有两个PN结的半导体器件。测试三极管要使用万用电表的欧姆挡，并选择R×100或R...
KG5 汽车电子
热门器件
热门资源推荐
LF356运算放大器PDF文档 地铁LED不间断应急照明系统设计 1)打开“聚类分析软件”文件夹 超级MCU单片机调试工具 HID调试 光电传感器.rar 全数字信号发生器的硬件设计 富士通变频器电路图方案 【实验107】24L01无线模块 数字电子技术基础（西北工业大学出版社+2003） 现代控制系统 国外计算机科学教材系列 (Richard C.Dorf Robert H.Bishop)
医疗电子设备小型化 2017年国赛电源本科类大家有什么想法吗？ 跟随器输出被放大，请指教 参会赢iPad2！Silicon Labs & EDOM新品巡演及应用技术研讨会，等你来！ 大家应该都碰到过这种情况，该怎么解决？？？？？ 帮忙看下这个USB插排哪里坏了？ 局域网内设备与个别上位机不互通 一个process不可以有两个时钟触发 关于 SD卡如何识别分区 SIM300C模块注册网络失败..江湖救急...
简洁的过零调功器电路设计与分析 单稳态控制电路设计与分析 光控电路设计与分析 永不缺相启动运行的电动机控制电路 IGBT模块通过控制门极阻断过电流 MT3608构成3.7V转12V的升压电路图 运算放大器IC741的基本工作原理及在电路中的实现方式 比较常见的功率整流器和滤波电路 一个简单的红外耳机电路 基于TDA1554的立体声放大器电路
器件捷径:
S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY
需要登录后才可以下载。
登录取消