HIGH-SPEED 64/32K x 8
SYNCHRONOUS
DUAL-PORT STATIC RAM
Features:
◆
◆
IDT709089/79S/L
◆
◆
◆
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 9/12/15ns (max.)
– Industrial: 12ns (max.)
Low-power operation
– IDT709089/79S
Active: 950mW (typ.)
Standby: 5mW (typ.)
– IDT709089/79L
Active: 950mW (typ.)
Standby: 1mW (typ.)
Flow-Through or Pipelined output mode on either port via
the
FT/PIPE
pin
Counter enable and reset features
◆
◆
◆
◆
◆
◆
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 4ns setup to clock and 1ns hold on all control, data,
and address inputs
– Data input, address, and control registers
– Fast 9ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 15ns cycle time, 66.7MHz operation in the Pipelined
output mode
TTL- compatible, single 5V (±10%) power supply
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Available in 100-pin Thin Quad Flatpack (TQFP) package
Green parts available, see ordering information
Functional Block Diagram
R/W
L
OE
L
CE
0L
CE
1L
R/W
R
OE
R
CE
0R
CE
1R
1
0
0/1
1
0
0/1
FT/PIPE
L
0/1
1
0
0
1
0/1
FT/PIPE
R
I/O
0L
- I/O
7L
I/O
Control
I/O
Control
I/O
0R
- I/O
7R
A
15L
(1)
A
0L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
A
15R
(1)
A
0R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
3242 drw 01
.
NOTE:
1. A
15X
is a NC for IDT709079.
FEBRUARY 2016
1
©2016 Integrated Device Technology, Inc.
DSC-3242/16
IDT709089/79S/L
High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description:
The IDT709089/79 is a high-speed 64/32K x 8 bit synchronous Dual-
Port RAM. The memory array utilizes Dual-Port memory cells to allow
simultaneous access of any address from both ports. Registers on control,
data, and address inputs provide minimal setup and hold times. The timing
latitude provided by this approach allows systems to be designed with very
short cycle times.
With an input data register, the IDT709089/79 has been optimized for
applications having unidirectional or bidirectional data flow in bursts.
An automatic power down feature, controlled by
CE
0
and CE
1,
permits
the on-chip circuitry of each port to enter a very low standby power
mode. Fabricated using CMOS high-performance technology, these
devices typically operate on only 950mW of power.
Pin Configuration
(1,2,3)
NC
NC
A
7R
A
8R
A
9R
A
10R
A
11R
A
12R
A
13R
A
14R
A
15R
NC
GND
NC
NC
NC
NC
CE
0R
CE
1R
CNTRST
R
R/W
R
OE
R
FT/PIPE
R
GND
NC
NC
NC
A
6R
A
5R
A
4R
A
3R
A
2R
A
1R
A
0R
CNTEN
R
CLK
R
ADS
R
GND
ADS
L
CLK
L
CNTEN
L
A
0L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
NC
NC
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
709089/79
(5)
PN100
20
21
22
23
10
11
12
13
14
15
16
17
18
19
24
25
26
NC
NC
NC
I/O
7R
I/O
6R
I/O
5R
I/O
4R
I/O
3R
V
CC
I/O
2R
I/O
1R
I/O
0R
GND
V
CC
I/O
0L
I/O
1L
GND
I/O
2L
I/O
3L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
NC
GND
3242 drw 02
1
2
3
4
5
6
7
8
Index
NOTES:
1. A
15X
is a NC for IDT709079.
2. All V
CC
pins must be connected to power supply.
3. All GND pins must be connected to ground supply.
4. Package body is approximately 14mm x 14mm x 1.4mm.
5. This package code is used to reference the package diagram.
NC
NC
A
7L
A
8L
A
9L
A
10L
A
11L
A
12L
A
13L
A
14L
A
15L
NC
V
CC
NC
NC
NC
NC
CE
0L
CE
1L
CNTRST
L
R/W
L
OE
L
FT/PIPE
L
NC
NC
9
6.42
2
IDT709089/79S/L
High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
CE
0L
, CE
1L
R/W
L
OE
L
A
0L
- A
15L
(1)
I/O
0L
- I/O
7L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
FT/PIPE
L
Right Port
CE
0R
, CE
1R
R/W
R
OE
R
A
0R
- A
15R
(1)
I/O
0R
- I/O
7R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
FT/PIPE
R
V
CC
GND
Names
Chip Enables
Read/Write Enable
Output Enable
Address
Data Input/Output
Clock
Address Strobe
Counter Enable
Counter Reset
Flow-Through/Pipeline
Power
Ground
3242 tbl 01
NOTE:
1. A
15X
is a NC for IDT709079.
Truth Table I—
Read/Write and Enable Control
(1,2,3)
OE
X
X
X
L
H
CLK
↑
↑
↑
↑
X
CE
0
H
X
L
L
L
CE
1
X
L
H
H
H
R/W
X
X
L
H
X
I/O
0-7
High-Z
High-Z
D
IN
D
OUT
High-Z
Mode
Deselected
Deselected
Write
Read
Outputs Disabled
3242 tbl 02
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2.
ADS, CNTEN, CNTRST
= X.
3.
OE
is an asynchronous input signal.
Truth Table II—Address Counter Control
(1,2)
External
Address
An
X
X
X
Previous
Internal
Address
X
An
An + 1
X
Internal
Address
Used
An
An + 1
An + 1
A
0
CLK
↑
↑
↑
↑
ADS
L
(4)
H
H
X
CNTEN
X
L
(5)
H
X
CNTRST
H
H
H
L
(4)
I/O
(3)
D
I/O
(n)
D
I/O
(n+1)
D
I/O
(n+1)
D
I/O
(0)
External Address Used
Counter Enabled—Internal Address generation
External Address Blocked—Counter disabled (An + 1 reused)
Counter Reset to Address 0
5640 tbl 03
MODE
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2.
CE
0
and
OE
= V
IL
; CE
1
and R/W = V
IH
.
3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle.
4.
ADS
is independent of all other signals including
CE
0
and CE
1
.
5. The address counter advances if
CNTEN
= V
IL
on the rising edge of CLK, regardless of all other signals including
CE
0
and CE
1
.
6.42
3
IDT709089/79S/L
High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Recommended Operating
Recommended DC Operating
(1)
Temperature and Supply Voltage
Conditions
Grade
Commercial
Industrial
Ambient
Temperature
0
O
C to +70
O
C
-40
O
C to +85
O
C
GND
0V
0V
V
CC
5.0V
+
10%
5.0V
+
10%
3242 tbl 04
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
-0.5
(2)
Typ.
5.0
0
____
____
Max.
5.5
0
6.0
(1)
0.8
Unit
V
V
V
V
3242 tbl 05
NOTES:
1. This is the parameter T
A
. This is the "instant on" case temperature.
NOTES:
1. V
TERM
must not exceed V
CC
+ 10%.
2. V
IL
> -1.5V for pulse width less than 10ns.
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
T
BIAS
T
STG
T
JN
I
OUT
Rating
Terminal Voltage
with Respect to GND
Temperature Under Bias
Storage Temperature
Junction Temperature
DC Output Current
Commercial
& Industrial
-0.5 to +7.0
-55 to +125
-65 to +150
+150
50
Unit
V
o
o
o
Capacitance
(1)
Symbol
C
IN
C
OUT
(3)
Parameter
Input Capacitance
(T
A
= +25°C, f = 1.0MH
z
)
Conditions
(2)
V
IN
= 3dV
V
OUT
= 3dV
Max.
9
10
Unit
pF
pF
3242 tbl 07
C
C
C
Output Capacitance
mA
3242 tbl 06
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output
switch from 0V to 3V or from 3V to 0V.
3. C
OUT
also references C
I/O
.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
TERM
must not exceed V
CC
+ 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> V
CC
+ 10%.
3. Ambient Temperature Under DC Bias. No AC Conditions. Chip Deselected.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(V
CC
= 5.0V ± 10%)
709089/79S/L
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
(1)
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Conditions
V
CC
= 5.5V, V
IN
= 0V to V
CC
CE
0
= V
IH
or CE
1
= V
IL
, V
OUT
= 0V to V
CC
I
OL
= +4mA
I
OH
= -4mA
Min.
___
___
___
Max.
10
10
0.4
___
Unit
µA
µA
V
V
3242 tbl 08
2.4
NOTE:
1. At V
CC
< 2.0V input leakages are undefined.
6.42
4
IDT709089/79S/L
High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(6)
(V
CC
= 5V ± 10%)
709089/79X9
Com'l Only
Symbol
I
CC
Parameter
Dynamic Operating
Current
(Both Ports Active)
Test Condition
CE
L
and
CE
R
= V
IL
Outputs Disabled
f = f
MAX
(1)
Version
COM'L
IND
COM'L
IND
CE
"A"
= V
IL
and
CE
"B"
= V
IH
(3)
Active Port Outputs
Disabled, f=f
MAX
(1)
Both Ports
CE
R
and
CE
L
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(2)
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(5)
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, Active Port Outputs
Disabled, f = f
MAX
(1)
COM'L
IND
COM'L
IND
COM'L
IND
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
Typ.
(4)
210
210
____
____
709089/79X12
Com'l
& Ind
Typ.
(4)
200
200
200
200
50
50
50
50
130
130
130
130
1.0
0.2
1.0
0.2
120
120
120
120
Max.
345
305
380
340
110
90
125
105
230
200
245
215
15
5
15
5
205
185
220
200
709089/79X15
Com'l Only
Typ.
(4)
190
190
____
____
Max.
390
350
____
____
Max.
325
285
____
____
Unit
mA
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
CE
L
=
CE
R
= V
IH
f = f
MAX
(1)
50
50
____
____
135
115
____
____
50
50
____
____
110
90
____
____
mA
I
SB2
Standby Current
(One Port - TTL
Level Inputs)
140
140
____
____
270
240
____
____
120
120
____
____
220
190
____
____
mA
I
SB3
Full Standby Current
(Both Ports -
CMOS Level Inputs)
1.0
0.2
____
____
15
5
____
____
1.0
0.2
____
____
15
5
____
____
mA
I
SB4
Full Standby Current
(One Port -
CMOS Level Inputs)
130
130
____
____
245
225
____
____
110
110
____
____
195
175
____
____
mA
3242 tbl 09
NOTES:
1. At f = f
MAX
, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/t
CYC
, using "AC TEST CONDITIONS" at input levels of
GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. V
CC
= 5V, TA = 25°C for Typ, and are not production tested. I
CC DC
(f=0) = 150mA (Typ).
5.
CE
X
= V
IL
means
CE
0X
= V
IL
and CE
1X
= V
IH
CE
X
= V
IH
means
CE
0X
= V
IH
or CE
1X
= V
IL
CE
X
< 0.2V means
CE
0X
< 0.2V and CE
1X
> V
CC
- 0.2V
CE
X
> V
CC
- 0.2V means
CE
0X
> V
CC
- 0.2V or CE
1X
< 0.2V
"X" represents "L" for left port or "R" for right port.
6. 'X' in part numbers indicate power (S or L).
6.42
5
FPGA/CPLD
