70P3337S233RM,70P3337S233RM pdf中文资料,70P3337S233RM引脚图,70P3337S233RM电路-Datasheet-电子工程世界

文档预览

1024K/512K x18

SYNCHRONOUS

DUAL QDR-II

PRELIMINARY DATASHEET

IDT70P3307

IDT70P3337

Features

◆

18Mb Density (1024K x 18)

– Also available 9Mb Density

(512K x 18)

QDR-II x 18 Burst-of-2 Interface

– Commercial: 233MHz, 250MHz

Separate, Independent Read and Write Data Ports

– Supports concurrent transactions

Dual Echo Clock Output

Two-Word Burst on all DPRAM accesses

DDR (Double Data Rate) Multiplexed Address Bus

– One Read and One Write request per clock cycle

DDR (Double Data Rate) Data Buses

– Four word burst data (Two Read and Two Write) per clock on

each port

◆

– Four word transfers per clock cycle per port (four word bursts

on 2 ports)

Port Enable pins (E

) for depth expansion

Dual Echo Clock Output with DLL-based phase alignment

High Speed Transceiver Logic inputs that can be scaled to

receive signals from 1.4V to 1.9V

Scalable output drivers

– Drives HSTL, 1.8V TTL or any voltage level from 1.4V to 1.9V

– Output impedance adjustable from 35 ohms to 70 ohms

1.8V Core Voltage (V

)

576-ball Flip Chip BGA (25mm x 25mm, 1.0mm ball pitch)

JTAG Interface - IEEE 1149.1 Compliant

Functional Block Diagram

REFL

P[1:0]

L[1:0]

WRITE

REFR

R[1:0]

0 L -

1 7 L

LEFT PORT

DATA

AND LOGIC

(1)

0 L -

1 7 L

C Q

WRITE DRIVER

RIGHT PORT

DATA

AND LOGIC

SELECT OUTPUT

0 R -

1 7 R

OUTPUT REGISTER

OUTPUT BUFFER

SELECT OUTPUT

SENSE AMPS

(1)

0 R -

1 7 R

C Q

MUX

1024/512K x 18

MEMORY

ARRAY

0L-

18L

(2)

0 L -

1 L

LEFT PORT

ADDRESS

AND LOGIC

ADDRESS DECODE

RIGHT PORT

ADDRESS

AND LOGIC

0R-

18R

(2)

0 R -

1 R

TCK

TMS

TR ST

TDI

REF

TDO

JTAG

6725 drw01

REF

NOTES:

1. Input pin to adjust the device outputs to the system data bus impedance.

2. Address A

is a INC for IDT70P3337. Disabled input pin (Diode tied to V

and V

January 29, 2009

NOT AN OFFER FOR SALE

The information

presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale

or an offer for sale that creates a contractual power of acceptance. "QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semicondor, IDT, and Micron Tecnology, Inc."

DSC-6725/1

18/9Mb QDR-II

x18 IDT70P3307/70P3337

SYNCHRONOUS Dual QDR-II

Preliminary Datasheet

Commercial Temperatue Range

Pin Configuration

70P3307

70P3337

RM-576 Ball Flip Chip BGA

Top View

A1 BALL PAD CORNER

INC

DDQR

REFR

INC

A12

A11

DDQR

A14

A13

A16

DDQR

A15

A18

A17

DDQR

INC

DDQR

M R ST D

OFFR

INC

DDQR

EPTH

INC

DDQR

INC

DDQR

A10

DDQR

INC

DDQR

INC

INC V

DDQR

INC

DDQR

INC V

DDQR

INC

DDQR

INC

DDQR

INC

D26

INC

REFR

INC V

DDQR

INC

DDQR

DDQL

DDQR

DDQL

DDQR

DDQL

Q16

Q14

Q12

Q10

Q16

Q14

Q12

Q17

Q15

Q13

Q11

Q17

Q15

Q13

DDQR

D15

REFR

DDQR

D16

DDQR

D13

D11

D14

DDQR

D12

DDQL

DDQR

DDQL

DDQR

D17

D10

DDQL

D16

DDQL

D15

D13

D14

DDQL

D12

DDQL

INC

DDQL

REFL

DDQL

Q10

Q11

INC

DDQL

TCK

DDQL

D11

DDQL

INC

D10

REFL

DDQL

INC

DDQL

TR ST

INC

REFL

INC

INC V

DDQL

INC

DDQL

A11

A12

DDQL

A16

A13

A14

DDQL

A17

A18

A15

DDQL

INC

INC V

DDQL

INC

DDQL

INC V

DDQL

TDI

TMS

DDQL

INC

DDQL

A10

INC

DDQL

EP1

OFFL

INC

TDO

6725 drw02

NOTE:

1. The package is 25mm x 25mm x 2.55mm with 1.0mm ball pitch; the customer will have to provide external airflow of 100LFM (0.5m/s) or higher at 250MHz.

January 29, 2009

18/9Mb QDR-II

x18 IDT70P3307/70P3337

SYNCHRONOUS Dual QDR-II

Preliminary Datasheet

Commercial Temperatue Range

Functional Description

As a memory standard, the (Quad Data Rate) QDR-II SRAM

interface has become increasingly common in high performance

networking systems. With the QDR-II interface/configuration, memory

throughput is increased without increasing the clock rate via the use

of two unidirectional buses on each of providing 2 ports of QDR-II

makes this a Dual-QDRII Static Ram two ports to transfer data without

the need for bus turnaround.

Dual QDR-II Static RAMs are high speed synchronous mem-

ories supporting two independent double-data-rate (DDR) read and

write data ports. This scheme allows simultaneous read and write

access for the maximum device throughput - two data items are

passed with each read or write. Four data word transfers occur per

clock cycle, providing quad-data-rate (QDR) performance on each

port. Comparing this with standard SRAM common I/O single data

rate (SDR) devices, a four to one increase in data access is achieved

at equivalent clock speeds. IDT70P3307/70P3337 Dual QDR-II Static

RAM devices, are capable of sustaining full bandwidth on both the

input and output buses simultaneously. Using independent buses for

read and write data access simplifies design by eliminating the need

for bidirectional buses. And all data are in two word bursts, with

addressing capability to the burst level.

Devices with QDR-II interfaces include network processor units

(NPUs) and field programmable gate arrays (FPGAs).

IDT70P3307/70P3337 Dual QDR-II Static RAMs support uni-

directional 18-bit read and write interfaces. These data inputs and

outputs operate simultaneously, thus eliminating the need for high-

speed bus turnarounds (i.e. no dead cycles are present). Access to

each port is accomplished using a common 18-bit address bus (17

bits for IDT70P3337). Addresses for reads and writes are latched on

rising edges of the K and

input clocks, respectively. The K and

clocks are offset by 90 degrees or half a clock cycle. Each address

location is associated with two 18-bit data words that burst sequentially

into or out of the device. Since data can be transferred into and out

of the device on every rising edge of the K and

clocks, memory

bandwidth is maximized while simplifying overall design through the

elimination of bus turnaround(s). IDT70P3307/70P3337 QDR-II Dual-

Port Static RAMs can support devices in a multi-drop configuration

(i.e. multiple devices connected to the same interface). Through this

capability, system designers can support compatible devices such as

NPUs and FPGAs on the same bus at the same time.

Using independent ports for read and write access simplifies

design by eliminating the need for bidirectional buses. All buses

associated with QDR-II Dual-Port Static RAMs are unidirectional and

can be optimized for signal integrity at very high bus speeds. The

QDR-II Dual-Port Static RAM has scalable output impedance on its

data output bus and echo clocks allowing the user to tune the bus for

low noise and high performance.

IDT70P3307/70P3337 Dual QDR-II Static RAMs have a single

DDR address bus per port with multiplexed read and write addresses.

All read addresses are received on the first half of the clock cycle and

all write addresses are received on the second half of the clock cycle.

The byte write signals are received on both halves of the clock cycle

simultaneously with the data they are controlling on the data input bus.

The Dual QDR-II Static RAM device has echo clocks, which

provide the user with a clock that is precisely timed to the data output

and tuned with matching impedance and signal quality. The user

can use the echo clock for downstream clocking of the data. For

the user, echo clocks eliminate the need to produce alternate clocks

with precise timing, positioning, and signal qualities to guarantee

data capture. Since the echo clocks are generated by the same

source that drives the data output, the relationship to the data is

NOT significantly affected by external parameters such as voltage,

temperature, and process as would be the case if the clock were

generated by an outside source. Thus the echo clocks are guar-

anteed to be synchronized with the data.

All interfaces of Dual QDR-II Static RAMs are HSTL, allow-

ing speeds beyond SRAM devices that use any form of TTL

interface. The interface can be scaled to higher voltages (up to

1.9V) to interface with 1.8V systems, if necessary. The device has

VDDQ pins and a separate Vref, allowing the user to designate the

interface operational voltage independent of the device core volt-

age of 1.8V VDD. Output impedance control pins allow the user

to adjust the drive strength to adapt to a wide range of loads and

transmission lines.

Clocking

The IDT70P3307/70P3337 has two sets of input clocks for

both the input and output, the K,

clocks and the C,

clocks. In

addition, the IDT70P3307/70P3337 has an output “echo” clock

pair, CQ and

CQ.

The K and

clocks are the primary device input clocks.

The K clock is used to clock in the control signals (R,

E[1:0],

BW0-1),

the read address, and the first word of the data burst

(D[17:0]) during a write operation. The

clock is used to clock in

the control signals (BW

0-1

, E[1:0]), write address and the second

word of the data burst during a write operation (D[17:0]). In the

event that the user disables the C and

clocks, the K and

clocks

will also be used to clock the data out of the output register and

generate the echo clocks. The K and

C and

C,CQ

and

CQ,

pairs

are offset by half a clock cycle from each other.

The C and

clocks may be used to clock the data out of

the output register during read operations and to generate the echo

clocks. C and

must be presented to the memory within the timing

tolerances as shown in the AC Electrical Characteristics Table

(Page 12). The output data from the IDT70P3307/70P3337 will be

closely aligned to the C and

input, through the use of an internal

DLL. When

is presented to the IDT70P3307/70P3337 the DLL

will have already internally clocked the data to arrive at the device

output simultaneously with the arrival of the

clock. The C and

second data item of the burst will also correspond.

Single Clock Mode

The IDT70P3307/70P3337 may be operated with a single

clock pair. C and

may be disabled by tying both signals high,

forcing the outputs and echo clocks to be controlled instead by the

K and

clocks.

DLL Operation

The DLL in the output structure of the IDT70P3307/70P3337

can be used to closely align the incoming clocks C and

with the

January 29, 2009

18/9Mb QDR-II

x18 IDT70P3307/70P3337

SYNCHRONOUS Dual QDR-II

Preliminary Datasheet

Commercial Temperatue Range

output of the data, generating very tight tolerances between the two.

The user may disable the DLL by holding

OFF

low. With the DLL off,

the C and

(or K and

if C and

are not used) will directly clock

the output register of the IDT70P3307/70P3337. With the DLL off,

there will be a propagation delay from the time the clock enters the

device until the data appears at the output. QDR-II becomes QDRI

with DLL off. First data out is referenced to C instead of

Echo Clock

The echo clocks, CQ and

CQ,

are generated by the C and

clocks (or K,

if C,

are disabled). The rising edge of C generates

the rising edge of CQ, and the falling edge of

CQ.

The rising edge of

generates the rising edge of

and the falling edge of CQ. This

scheme improves the correlation of the rising and falling edges of the

echo clock and will improve the duty cycle of the individual signals.

The echo clock is very closely aligned with the data, guaran-

teeing that the echo clock will remain closely correlated with the data,

within the tolerances designated.

Normal QDR-II Read and Write Operations

The IDT70P3307/70P3337 Dual QDR-II Static RAM sup-

ports QDR-II burst-of-two read/write operations. Read operations are

initiated by holding the read port select (R) low, and presenting the

read address to the address port during the rising edge of K which

will latch the address. Data is delivered after the next rising edge of

the next

(t + 1), using C and

as the output timing references; or

K and

if C and

are tied high.

The write operation is a standard QDR-II burst-of-two write

operation, except the data is not available to be read until the next

clock cycle (this is one cycle later than standard QDR-II SRAM).

Normal QDR write cycles are initiated by holding the write port select

(W) low at K rising edge. Also, the Byte Write inputs (BW0-1),

designating which bytes are to be written, need to be held low for both

the K and

clocks. On the rising edge of K the first word of the data

must also be present on the data input bus D[17:0] observing the

designated set up times. Upon the rising edge of K the first word of

the burst will be latched into the input register. After K has risen, and

the designated hold times observed, the second half of the clock cycle

is initiated by presenting the write address to the address bus A[X:0],

the

BW0-1

inputs for the second data word of the burst, and the second

data item of the burst to the data bus D[17:0]. Upon the rising edge

the second word of the burst will be latched, along with the

designated address. Both the first and second words of the burst will

be written into memory as designated by the address and byte write

enables. The addresses for the write cycles is provided at the

rising

edge, and data is expected at the rising edge of K and

beginning

at the same K that initiated the cycle.

Programmable Impedance

An external resistor, RQ, must be connected between the

ZQ pin on the IDT70P3307/70P3337 and tied to V

to allow the

IDT70P3307/70P3337 to adjust its output drive impedance. The value

of RQ must be 5X the value of the intended drive impedance of the

IDT70P3307/70P3337. The allowable range of RQ to guarantee

impedance matching with a tolerance of +/- 15% is 175 ohms to 350

ohms. The output impedance is adjusted every 1024 clock cycles to

correct for drifts in supply voltage and temperature. If the user wishes

to drive the output impedance of the IDT70P3307/70P3337 to its

lowest value, the ZQ pin may be tied to V

DDQ

January 29, 2009

18/9Mb QDR-II

x18 IDT70P3307/70P3337

SYNCHRONOUS Dual QDR-II

Preliminary Datasheet

Commercial Temperatue Range

Pin Definitions

andSymbol

Pin Function

Input

Synchronous

Input

Synchronous

Input

Synchronous

Output

Synchronous

Input

Synchronous

Input

Synchronous

Input Clock

Output Clock

Description

Data input signals, sampled on the rising edge of K and

clocks during valid write operations

Byte Write Selects active LOW. Sampled on the rising edge of the K and again on the rising edge of

clocks during write operations. Used to select which byte is

written into the device during the current portion of the write operations. Bytes not written remain unaltered. All byte writes are sampled on the same edge as the

data. Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and not written in to the device.

controls D[8:0],

controls D[17:9].

Address Inputs. Read addresses are sampled on the rising edge of K clock during active read operations. Write addresses are sampled on the rising edge of

clock during active write operations. These address inputs are multiplxed, so that both a read and write operation can occur on the same clock cycle. These inputs

are ignored when the appropriate port is deselected.

Data Output signals. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising edge of both the C and

clocks during

Read operations or K and

when operating in single clock mode. When the Read port is deselected, Q[17:0] are automatically tri-stated.

Write Control Logic, active LOW. Sampled on the rising edge of the positive input clock (K). When asserted active, a write operation in initiated. Deasserting will

deselect the Write port. Deselecting the Write port will cause D[17:0] to be ignored.

Read Control Logic, active LOW. Sampled on the rising edge of Positive Input Clock (K). When active, a Read operation is initiated. Deasserting will cause the

Read port to be deselected. When deselected, the pending access is allowed to complete and the output drivers are automatically tri-stated following the next

rising edge of the

clock. (D

OFFX

= 1). Each read access consists of a burst of two sequential transfers.

Positive Output Clock Input. C is used in conjunction with

to clock out the Read data from the device. C and

can be used together to deskew the flight times of

various devices on the board back to the controller. See application example for further details.

Negative Output Clock Input.

is used in conjunction with C to clock out the Read data from the device. C and

can be used together to deskew the flight times

of various devices on the board back to the controller. See application example for further details.

Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device. Drives out data through Q[17:0] when in single clock mode.

All accesses are initiated on the rising edge of K.

Negative Input Clock Input.

is used to capture synchronous inputs being presented to the device. Drives out data through Q[17:0] when in single clock mode.

Synchronous Echo clock output. The rising edge of CQ is tightly matched to the synchronous data outputs and can be used as a data valid indication. CQ is free

running and does not stop when the output data is tri-stated.

Synchronous Echo Clock output. The rising edge of

is tightly matched to the synchronous data outputs and can be used as a data valid indication.

is free

running and does not stop wehen the output data is tri-stated.

Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. Q[17:0] output impedance is set to 0.2 x RQ,

where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be connected directly to V

DDQ

, which enables the minimum impedance mode.

This pin cannot be connected directly to GND or left unconnected.

EP[1:0] are used to program the Port Enable pins E[1:0]. EP[1:0] are programmed by tying the pins high or low on the board. If a customer does not want to use

Pins EP[1:0], then these pins should be tied low. Refer to Truth Table III for Port Enable pins.

Two Port Enable pins E[1:0] are provided to connect to the two MSB bits on the memory controller in order to cascade up to four IDT70P3307 devices. If a customer

does not want to use Pins E[1:0], then these pins should be tied low. Refer to Truth Table III for Port Enable pins. Also refer to Figure 1 showing cascade/multi-drop

using port-enable (E[1:0]) pins. E[1:0] are sampled on the rising edge of K for read operations and again on rising edge of

for write operations.

DLL Turn Off. When low this input will turn off the DLL inside the device. The AC timings with the DLL turned off will be different from those listed in this data sheet.

There will be an increased propagation delay from the incidence of C and

to Q, or K and

to Q as configured.

Master Reset pin. When held low will reset the device.

The DEPTH pin selects between the 18Mb and the 9Mb density, and it needs to be tied to V

DEPTH = V

puts the device in a 9Mb configuration.

TDO pin for JTAG.

TCK pin for JTAG.

TDI pin for JTAG.

TMS pin for JTAG.

Reset pin for JTAG.

Should be tied to V

or V

only, or can be left as a floating pin.

D[17:0]

A[18:0]

X(2)

Q[17:0]

Output Clock

Input

EP[1:0]

[1:0]

Input

Syncronous

OFFX

MRST

Input

Asynchronous

Input

Output

Input

Asynchronous

DEPTH

TDO

TCK

TDI

TMS

TRST

INC

REF

DDQX

Vss. DEPTH = Vss puts the device in the 18Mb configuration, and

Input

Reference

Power Supply

Ground

Power Supply

Reference Voltage input. Static input used to set the reference level for HSTL inputs as well as AC measurement points.

Power supply inputs to the core of the device. Should be connected to a 1.8V power supply.

Ground for the device. Should be connected to ground of the system.

Power supply for the outputs of the device. Should be connected to a 1.5V power supply for HSTL or scaled to the desired output voltage.

6725 tbl01

NOTES:

1. "

" = "

" for the Left Port pins and "

" = "

" for the Right Port pins.

2. A[17:0]x for IDT70P3337.

January 29, 2009

型号	70P3337S233RM	70P3337S250RM	70P3307S233RM	70P3307S233RMI	70P3337S233RMI	70P3337S200RMI	70P3307S250RM
描述	FCBGA-576, Tray	FCBGA-576, Tray	FCBGA-576, Tray	FCBGA-576, Tray	FCBGA-576, Tray	FCBGA-576, Tray	FCBGA-576, Tray
Brand Name	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology
是否无铅	含铅	含铅	含铅	含铅	含铅	含铅	含铅
是否Rohs认证	符合	符合	符合	符合	符合	符合	符合
厂商名称	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
零件包装代码	FCBGA	FCBGA	FCBGA	FCBGA	FCBGA	FCBGA	FCBGA
针数	576	576	576	576	576	576	576
制造商包装代码	RM576	RM576	RM576	RM576	RM576	RM576	RM576
Reach Compliance Code	_compli	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant
包装说明	BGA,	BGA,	BGA,	BGA,	BGA,	-	BGA,
ECCN代码	3A991	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	-	3A991.B.2.A
最长访问时间	0.45 ns	0.45 ns	-	0.45 ns	0.45 ns	-	0.45 ns
JESD-30 代码	S-PBGA-B576	S-PBGA-B576	-	S-PBGA-B576	S-PBGA-B576	-	S-PBGA-B576
JESD-609代码	e1	e1	-	e1	e1	e1	e1
长度	25 mm	25 mm	-	25 mm	25 mm	-	25 mm
内存密度	9437184 bi	9437184 bit	-	18874368 bit	9437184 bit	-	18874368 bit
内存集成电路类型	QDR SRAM	QDR SRAM	-	QDR SRAM	QDR SRAM	QDR SRAM	QDR SRAM
内存宽度	18	18	-	18	18	-	18
湿度敏感等级	4	4	-	4	4	4	4
功能数量	1	1	-	1	1	-	1
端子数量	576	576	-	576	576	-	576
字数	524288 words	524288 words	-	1048576 words	524288 words	-	1048576 words
字数代码	512000	512000	-	1000000	512000	-	1000000
工作模式	SYNCHRONOUS	SYNCHRONOUS	-	SYNCHRONOUS	SYNCHRONOUS	-	SYNCHRONOUS
最高工作温度	70 °C	70 °C	-	85 °C	85 °C	-	70 °C
组织	512KX18	512KX18	-	1MX18	512KX18	-	1MX18
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY
封装代码	BGA	BGA	-	BGA	BGA	-	BGA
封装形状	SQUARE	SQUARE	-	SQUARE	SQUARE	-	SQUARE
封装形式	GRID ARRAY	GRID ARRAY	-	GRID ARRAY	GRID ARRAY	-	GRID ARRAY
并行/串行	PARALLEL	PARALLEL	-	PARALLEL	PARALLEL	-	PARALLEL
峰值回流温度（摄氏度）	245	245	-	245	245	245	245
认证状态	Not Qualified	Not Qualified	-	Not Qualified	Not Qualified	-	Not Qualified
座面最大高度	2.55 mm	2.55 mm	-	2.55 mm	2.55 mm	-	2.55 mm
最大供电电压 (Vsup)	1.9 V	1.9 V	-	1.9 V	1.9 V	-	1.9 V
最小供电电压 (Vsup)	1.7 V	1.7 V	-	1.7 V	1.7 V	-	1.7 V
标称供电电压 (Vsup)	1.8 V	1.8 V	-	1.8 V	1.8 V	-	1.8 V
表面贴装	YES	YES	-	YES	YES	-	YES
技术	CMOS	CMOS	-	CMOS	CMOS	-	CMOS
温度等级	COMMERCIAL	COMMERCIAL	-	INDUSTRIAL	INDUSTRIAL	-	COMMERCIAL
端子面层	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	-	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式	BALL	BALL	-	BALL	BALL	-	BALL
端子节距	1 mm	1 mm	-	1 mm	1 mm	-	1 mm
端子位置	BOTTOM	BOTTOM	-	BOTTOM	BOTTOM	-	BOTTOM
处于峰值回流温度下的最长时间	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
宽度	25 mm	25 mm	-	25 mm	25 mm	-	25 mm