70T3399S133BFG,70T3399S133BFG pdf中文资料,70T3399S133BFG引脚图,70T3399S133BFG电路-Datasheet-电子工程世界

文档预览

HIGH-SPEED 2.5V

512/256/128K X 18

IDT70T3339/19/99S

SYNCHRONOUS

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

Features:

◆

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed data access

– Commercial: 3.4 (200MHz)/3.6ns (166MHz)/

4.2ns (133MHz)(max.)

– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)

Selectable Pipelined or Flow-Through output mode

Counter enable and repeat features

Dual chip enables allow for depth expansion without

additional logic

Interrupt and Collision Detection Flags

Full synchronous operation on both ports

– 5ns cycle time, 200MHz operation (14Gbps bandwidth)

– Fast 3.4ns clock to data out

– Data input, address, byte enable and control registers

◆

– 1.5ns setup to clock and 0.5ns hold on all control, data,

and address inputs @ 200MHz

– Self-timed write allows fast cycle time

Separate byte controls for multiplexed bus and bus

matching compatibility

Dual Cycle Deselect (DCD) for Pipelined Output Mode

2.5V (±100mV) power supply for core

LVTTL compatible, selectable 3.3V (±150mV) or 2.5V

(±100mV) power supply for I/Os and control signals on

each port

Industrial temperature range (-40°C to +85°C) is

available at 166MHz and 133MHz

Available in a 256-pin Ball Grid Array (BGA) and 208-pin fine

pitch Ball Grid Array (fpBGA)

Supports JTAG features compliant with IEEE 1149.1

Green parts available, see ordering information

Functional Block Diagram

FT/PIPE

1/0

0a 1a

0b 1b

1b 0b

1a 0a

1/0

FT/PIPE

R/W

1/0

B B

0 1

L L

B B

1 0

R R

1/0

R/W

Dout0-8_L

Dout9-17_L

Dout0-8_R

Dout9-17_R

1b 0b 1a 0a

FT/PIPE

0/1

0a 1a 0b

0/1

FT/PIPE

512/256/128K x 18

MEMORY

ARRAY

I/O

- I/O

17L

Din_L

Din_R

I/O

- I/O

17R

CLK

18L

(1)

REPEAT

ADS

CNTEN

18R (1)

CLK

Counter/

Address

Reg.

ADDR_L

ADDR_R

Counter/

Address

Reg.

REPEAT

ADS

CNTEN

TDI

TCK

TMS

TRST

0 L

CE1L

INTERRUPT

COLLISION

DETECTION

LOGIC

0 R

CE1R

JTAG

TDO

COL

INT

(2)

COL

INT

CONTROL

LOGIC

(2)

5652 drw 01

NOTES:

1. Address A

is a NC for the IDT70T3319. Also, Addresses A

and A

are NC's for the IDT70T3399.

2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and

OPTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode.

APRIL 2010

DSC-5652/7

IDT70T3339/19/99S

High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Description:

The IDT70T3339/19/99 is a high-speed 512/256/128k x 18 bit

synchronous Dual-Port RAM. The memory array utilizes Dual-Port

memory cells to allow simultaneous access of any address from both ports.

Registers on control, data, and address inputs provide minimal setup and

hold times. The timing latitude provided by this approach allows systems

to be designed with very short cycle times. With an input data register, the

IDT70T3339/19/99 has been optimized for applications having unidirec-

tional or bidirectional data flow in bursts. An automatic power down feature,

controlled by

and CE

permits the on-chip circuitry of each port to

enter a very low standby power mode.

The IDT70T3339/19/99 can support an operating voltage of either

3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power

supply for the core of the device (V

) is at 2.5V.

6.42

IDT70T3339/19/99S

High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Pin Configuration

(3,4,5,6,9)

70T3339/19/99BC

BC-256

(8)

01/13/03

256-Pin BGA

Top View

(9)

A10

A11

A12

A13

A14

A15

A16

TDI

17L

(2)

14L

11L

CNTEN

B10

B11

B12

B13

B14

B15

B16

INT

TDO A

18L

(1)

15L

12L

R/W

REPEAT

C10

C11

C12

C13

C14

C15

C16

COL

I/O

16L

13L

10L

CLK

ADS

D10

D11

D12

D13

OPT

D14

D15

I/O

D16

I/O

PIPE/

DDQL

DDQR

DDQL

DDQR

E10

E11

E12

E13

E14

E15

I/O

E16

I/O

10R

I/O

10L

DDQL

F10

F11

DDQR

F12

F13

F14

I/O

F15

F16

I/O

11L

I/O

11R

DDQL

G10

G11

DDQR

I/O

G12

G13

G14

G15

I/O

G16

I/O

12L

DDQR

H10

H11

H12

DDQL

I/O

H13

H14

H15

H16

I/O

12R

NC V

DDQR

J10

J11

J12

DDQL

J13

J14

J15

I/O

J16

I/O

13L

I/O

14R

I/O

13R

DDQL

K10

K11

DDQR

I/O

K12

K13

K14

K15

K16

I/O

14L

DDQL

L10

L11

L12

DDQR

L13

L14

L15

I/O

L16

I/O

15L

I/O

15R

DDQR

M10

M11

M12

DDQL

I/O

M13

M14

M15

I/O

M16

I/O

16R

I/O

16L

NC V

DDQR

N10

N11

N12

DDQL

I/O

N13

N14

I/O

N15

N16

I/O

17R

PIPE/

DDQR

DDQL

DDQR

DDQL

P10

P11

P12

P13

P14

I/O

P15

P16

COL

I/O

17L

TMS

16R

18R

(1)

13R

10R

CLK

ADS

R10

R11

R12

R13

R14

R15

I/O

R16

INT

TRST

15R

12R

R/W

REPEAT

T10

T11

T12

T13

OPT

T14

T15

T16

TCK

17R

(2)

14R

11R

CNTEN

5652 drw 02d

NOTES:

1. Pin is a NC for IDT70T3319 and IDT70T3399.

2. Pin is a NC for IDT70T3399.

3. All V

pins must be connected to 2.5V power supply.

4. All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

(2.5V), and 2.5V if OPT pin for that port is

set to V

(0V).

5. All V

pins must be connected to ground supply.

6. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.

7. This package code is used to reference the package diagram.

8. This text does not indicate orientation of the actual part-marking.

9. Pins A15 and T15 will be V

REFL

and V

REFR

respectively for future HSTL device.

6.42

IDT70T3339/19/99S

High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Pin Configurations(con't)

(3,4,5,6,9)

01/13/03

I/O

INT

TDO

16L

12L

10 11

CLK

CNTEN

13 14

OPT

16 17

COL

TDI

17L(2)

13L

ADS

DDQR

I/O

DDQL

I/O

DDQR

PIPE/

18L(1)

14L

10L

R/W

I/O

10L

15L

11L

REPEAT

DDQL

I/O

11L

DDQR

I/O

10R

I/O

DDQL

I/O

11R

I/O

DDQR

I/O

12L

DDQL

I/O

DDQR

I/O

12R

70T3339/19/99BF

BF-208

(7)

208-Pin fpBGA

Top View

(8)

I/O

DDQL

DDQR

I/O

14R

I/O

13R

I/O

DDQL

I/O

14L

DDQR

I/O

13L

I/O

DDQL

I/O

15R

I/O

DDQR

I/O

15L

I/O

DDQL

I/O

16R

I/O

16L

DDQR

COL

TRST

16R

12R

CLK

CNTEN

I/O

17R

TCK

17R(2)

13R

ADS

DDQL

I/O

DDQR

I/O

17L

DDQL

TMS

18R(1)

14R

10R

R/W

INT

PIPE/

15R

11R

REPEAT

OPT

I/O

5652 drw 02c

NOTES:

1. Pin is a NC for IDT70T3319 and IDT70T3399.

2. Pin is a NC for IDT70T3399.

3. All V

pins must be connected to 2.5V power supply.

4. All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

(2.5V), and 2.5V if OPT pin for that port is

set to V

(0V).

5. All V

pins must be connected to ground supply.

6. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.

7. This package code is used to reference the package diagram.

8. This text does not indicate orientation of the actual part-marking.

9. Pins B14 and R14 will be V

REFL

and V

REFR

respectively for future HSTL device.

6.42

IDT70T3339/19/99S

High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Pin Names

Left Port

R/W

- A

18L

(5)

I/O

- I/O

17L

CLK

PL/FT

ADS

CNTEN

REPEAT

DDQL

OPT

TDI

TCK

TMS

TRST

INT

COL

INT

COL

Right Port

R/W

- A

18R

(5)

I/O

- I/O

17R

CLK

PL/FT

ADS

CNTEN

REPEAT

DDQR

OPT

Names

Chip Enables (Input)

(6)

Read/Write Enable (Input)

Output Enable (Input)

Address (Input)

Data Input/Output

Clock (Input)

Pipeline/Flow-Through (Input)

Address Strobe Enable (Input)

Counter Enable (Input)

Counter Repeat

(3)

Upper Byte Enable (I/O

- I/O

)

(6)

Lower Byte Enable (I/O

- I/O

)

(6)

Power (I/O Bus) (3.3V or 2.5V)

(1)

(Input)

Option for selecting V

DDQX

(1,2)

(Input)

Sleep Mode pin

(4)

(Input)

Power (2.5V)

(1)

(Input)

Ground (0V) (Input)

Test Data Input

Test Data Output

Test Logic Clock (10MHz) (Input)

Test Mode Select (Input)

Reset (Initialize TAP Controller) (Input)

Interrupt Flag (Output)

Collision Alert (Output)

5652 tbl 01

NOTES:

1. V

, OPT

, and V

DDQX

must be set to appropriate operating levels prior to

applying inputs on the I/Os and controls for that port.

2. OPT

selects the operating voltage levels for the I/Os and controls on that port.

If OPT

is set to V

(2.5V), then that port's I/Os and controls will operate at 3.3V

levels and V

DDQX

must be supplied at 3.3V. If OPT

is set to V

(0V), then that

port's I/Os and address controls will operate at 2.5V levels and V

DDQX

must be

supplied at 2.5V. The OPT pins are independent of one another—both ports can

operate at 3.3V levels, both can operate at 2.5V levels, or either can operate

at 3.3V with the other at 2.5V.

3. When

REPEAT

is asserted, the counter will reset to the last valid address loaded

via

ADS

4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when

asserted. All static inputs, i.e., PL/FTx and OPTx and the sleep mode pins

themselves (ZZx) are not affected during sleep mode. It is recommended that

boundry scan not be operated during sleep mode.

5. Address A

18x

is a NC for the IDT70T3319. Also, Addresses A

18x

and A

17x

are

NC's for the IDT70T3399.

6. Chip Enables and Byte Enables are double buffered when PL/FT = V

, i.e., the

signals take two cycles to deselect.

6.42