70V7319S166DD,70V7319S166DD pdf中文资料,70V7319S166DD引脚图,70V7319S166DD电路-Datasheet-电子工程世界

文档预览

HIGH-SPEED 3.3V 256K x 18

SYNCHRONOUS

BANK-SWITCHABLE

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

Features:

◆

IDT70V7319S

◆

256K x 18 Synchronous Bank-Switchable Dual-ported

SRAM Architecture

–

64 independent 4K x 18 banks

– 4 megabits of memory on chip

Bank access controlled via bank address pins

High-speed data access

– Commercial: 3.4ns (200MHz)/3.6ns (166MHz)/

4.2ns (133MHz) (max.)

– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)

Selectable Pipelined or Flow-Through output mode

Counter enable and repeat features

Dual chip enables allow for depth expansion without

additional logic

Full synchronous operation on both ports

– 5ns cycle time, 200MHz operation (14Gbps bandwidth)

– Fast 3.4ns clock to data out

– 1.5ns setup to clock and 0.5ns hold on all control, data, and

address inputs @ 200MHz

◆

– Data input, address, byte enable and control registers

– Self-timed write allows fast cycle time

Separate byte controls for multiplexed bus and bus

matching compatibility

LVTTL- compatible, 3.3V (±150mV) power supply

for core

LVTTL compatible, selectable 3.3V (±150mV) or 2.5V

(±100mV) power supply for I/Os and control signals on

each port

Industrial temperature range (-40°C to +85°C) is

available at 166MHz and 133MHz

Available in a 144-pin Thin Quad Flatpack (TQFP),

208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball

Grid Array (BGA)

Supports JTAG features compliant with IEEE 1149.1

–

Due

to limited pin count, JTAG is not supported on the

144-pin TQFP package.

Functional Block Diagram

PL/FT

OPT

CLK

ADS

CNTEN

REPEAT

R/W

PL/FT

OPT

CLK

ADS

CNTEN

REPEAT

R/W

CONTROL

LOGIC

MUX

4Kx18

MEMORY

ARRAY

(BANK 0)

MUX

CONTROL

LOGIC

I/O

0L-17L

I/O

CONTROL

MUX

4Kx18

MEMORY

ARRAY

(BANK 1)

MUX

I/O

CONTROL

I/O

0R-17R

11L

ADDRESS

DECODE

ADDRESS

DECODE

11R

BANK

DECODE

MUX

4Kx18

MEMORY

ARRAY

(BANK 63)

BANK

DECODE

NOTE:

1. The Bank-Switchable dual-port uses a true SRAM

core instead of the traditional dual-port SRAM core.

As a result, it has unique operating characteristics.

Please refer to the functional description on page 19

for details.

MUX

TDI

TDO

JTAG

TMS

TCK

TRST

5629 drw 01

JANUARY 2009

DSC 5629/8

IDT70V7319S

High-Speed 256K x 18 Synchronous Bank-Switchable Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Description:

The IDT70V7319 is a high-speed 256Kx18 (4Mbit) synchronous

Bank-Switchable Dual-Ported SRAM organized into 64 independent

4Kx18 banks. The device has two independent ports with separate

control, address, and I/O pins for each port, allowing each port to access

any 4Kx18 memory block not alReady accessed by the other port.

Accesses by the ports into specific banks are controlled via the bank

address pins under the user's direct control.

Registers on control, data, and address inputs provide minimal setup

and hold times. The timing latitude provided by this approach allows

systems to be designed with very short cycle times. With an input data

unidirectional or bidirectional data flow in bursts. An automatic power down

feature, controlled by CE

and CE

, permits the on-chip circuitry of each

port to enter a very low standby power mode. The dual chip enables also

facilitate depth expansion.

The 70V7319 can support an operating voltage of either 3.3V or 2.5V

on one or both ports, controllable by the OPT pins. The power supply for

the core of the device(V

) remains at 3.3V. Please refer also to the

functional description on page 19.

Pin Configuration

(1,2,3,4)

11/20/01

A10

A11

A12

A13

A14

A15

A16

A17

TDO

B10

CLK

CNTEN

B11

B12

B13

B14

OPT

B15

B16

B17

TDI

C10

ADS

C11

C12

C13

C14

DDQR

I/O

C15

C16

C17

DDQL

I/O

DDQR

PL/

10L

D10

R/W

D11

D12

D13

D14

I/O

D15

D16

D17

I/O

10L

11L

REPEAT

E14

DDQL

I/O

E15

E16

I/O

E17

I/O

11L

DDQR

I/O

10R

I/O

F14

F15

F16

F17

DDQL

I/O

11R

G14

I/O

G15

G16

DDQR

G17

I/O

12L

DDQL

I/O

H15

H16

H17

DDQR

I/O

12R

70V7319BF

BF-208

(5)

208-Pin fpBGA

Top View

(6)

H14

J14

J15

J16

I/O

J17

DDQL

K14

K15

DDQR

K16

K17

I/O

14R

I/O

13R

I/O

DDQL

I/O

L14

L15

L16

L17

I/O

14L

DDQR

I/O

13L

M14

I/O

M15

M16

I/O

M17

DDQL

I/O

15R

N14

N15

I/O

DDQR

N16

N17

I/O

15L

P10

P11

P12

P13

I/O

DDQL

P14

P15

P16

I/O

P17

I/O

16R

I/O

16L

DDQR

TRST

R10

CLK

CNTEN

R11

R12

R13

R14

I/O

R15

R16

R17

I/O

17R

TCK

T10

ADS

T11

T12

T13

T14

DDQL

I/O

DDQR

T15

T16

T17

I/O

17L

DDQL

TMS

10R

U10

R/W

U12

U13

U14

U15

U16

U17

PL/

11R

OPT

I/O

5629 drw 02c

NOTES:

1. All V

pins must be connected to 3.3V power supply.

2. All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

(3.3V), and 2.5V if OPT pin for that port is

set to V

(0V).

3. All V

pins must be connected to ground supply.

4. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.

5. This package code is used to reference the package diagram.

6. This text does not indicate orientation of the actual part-marking.

6.42

IDT70V7319S

High-Speed 256K x 18 Synchronous Bank-Switchable Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Pin Configuration

(1,2,3,4)

(con't.)

70V7319BC

BC-256

(5)

256-Pin BGA

Top View

(6)

A10

A11

A12

A13

A14

A15

A16

11/20/01

TDI

11L

B10

CNTEN

B11

B12

B13

B14

B15

B16

TDO

R/W

REPEAT

C10

C11

C12

C13

C14

C15

C16

I/O

10L

CLK

ADS

D10

D11

D12

D13

OPT

D14

D15

I/O

D16

I/O

PL/

DDQL

DDQR

DDQL

DDQR

E10

E11

E12

E13

E14

E15

I/O

E16

I/O

10R

I/O

10L

DDQL

F10

F11

DDQR

F12

F13

F14

I/O

F15

I/O

F16

I/O

11L

I/O

11R

DDQL

G10

G11

DDQR

I/O

G12

G13

G14

G15

I/O

G16

I/O

12L

DDQR

H10

H11

H12

DDQL

I/O

H13

H14

H15

H16

I/O

12R

DDQR

J10

J11

J12

DDQL

J13

J14

J15

I/O

J16

I/O

13L

I/O

14R

I/O

13R

DDQL

K10

K11

K12

DDQR

I/O

K13

K14

K15

I/O

K16

I/O

14L

DDQL

L10

L11

L12

DDQR

L13

L14

L15

I/O

L16

I/O

15L

I/O

15R

DDQR

M10

M11

M12

DDQL

I/O

M13

M14

M15

I/O

M16

I/O

16R

I/O

16L

DDQR

N10

N11

N12

DDQL

I/O

N13

N14

I/O

N15

N16

I/O

17R

PL/

DDQR

DDQL

DDQR

DDQL

P10

P11

P12

P13

P14

I/O

P15

P16

I/O

17L

TMS

10R

CLK

ADS

R10

R11

R12

R13

R14

R15

I/O

R16

TRST

R/W

REPEAT

T10

T11

T12

T13

OPT

T14

T15

T16

TCK

11R

CNTEN

5629 drw 02d

NOTES:

1. All V

pins must be connected to 3.3V power supply.

2. All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

(3.3V), and 2.5V if OPT pin for that port is

set to V

(0V).

3. All V

pins must be connected to ground supply.

4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.

5. This package code is used to reference the package diagram.

6. This text does not indicate orientation of the actual part-marking.

6.42

IDT70V7319S

High-Speed 256K x 18 Synchronous Bank-Switchable Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Pin Configuration

(1,2,3,4,7)

(con't.)

11/20/01

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

PL/FT

11L

10L

CLK

R/W

ADS

CNTEN

REPEAT

DDQR

I/O

10L

I/O

10R

I/O

11L

I/O

11R

DDQL

I/O

12L

I/O

12R

DDQR

DDQL

I/O

13R

I/O

13L

I/O

14R

I/O

14L

DDQR

I/O

15R

I/O

15L

I/O

16R

I/O

16L

I/O

17R

I/O

17L

DDQL

70V7319DD

DD-144

(5)

144-Pin TQFP

Top View

(6)

108

107

106

105

104

103

102

101

100

OPT

DDQR

I/O

DDQL

I/O

DDQR

DDQL

I/O

DDQR

I/O

DDQL

OPT

PT/FTR

11R

10R

CLK

R/W

ADS

CNTEN

REPEAT

5629 drw 02a

NOTES:

1. All V

pins must be connected to 3.3V power supply.

2. All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

(3.3V), and 2.5V if OPT pin for that port is set to V

(0V).

3. All V

pins must be connected to ground supply.

4. Package body is approximately 20mm x 20mm x 1.4mm.

5. This package code is used to reference the package diagram.

6. This text does not indicate orientation of the actual part-marking.

7. Due to the limited pin count, JTAG is not supported in the DD-144 package.

6.42

IDT70V7319S

High-Speed 256K x 18 Synchronous Bank-Switchable Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Pin Names

Left Port

R/W

- BA

- A

11L

I/O

- I/O

17L

CLK

PL/FT

ADS

CNTEN

REPEAT

DDQL

OPT

TDI

TDO

TCK

TMS

TRST

Right Port

R/W

- BA

- A

11R

I/O

- I/O

17R

CLK

PL/FT

ADS

CNTEN

REPEAT

DDQR

OPT

Chip Enables

Read/Write Enable

Output Enable

Bank Address

(4)

Address

Data Input/Output

Clock

Pipeline/Flow-Through

Address Strobe Enable

Counter Enable

Counter Repeat

(3)

Byte Enables (9-bit bytes)

Power (I/O Bus) (3.3V or 2.5V)

(1)

Option for selecting V

DDQX

(1,2)

Power (3.3V)

(1)

Ground (0V)

Test Data Input

Test Data Output

Test Logic Clock (10MHz)

Test Mode Select

Reset (Initialize TAP Controller)

5629 tbl 01

Names

NOTES:

1. V

, OPT

, and V

DDQX

must be set to appropriate operating levels prior to

applying inputs on the I/Os and controls for that port.

2. OPT

selects the operating voltage levels for the I/Os and controls on that port.

If OPT

is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V

levels and V

DDQX

must be supplied at 3.3V. If OPT

is set to VIL (0V), then that

port's I/Os and address controls will operate at 2.5V levels and V

DDQX

must be

supplied at 2.5V. The OPT pins are independent of one another—both ports can

operate at 3.3V levels, both can operate at 2.5V levels, or either can operate

at 3.3V with the other at 2.5V.

3. When

REPEAT

is asserted, the counter will reset to the last valid address loaded

via

ADS

4. Accesses by the ports into specific banks are controlled by the bank address

pins under the user's direct control: each port can access any bank of memory

with the shared array that is not currently being accessed by the opposite port

(i.e., BA

- BA

≠

- BA

). In the event that both ports try to access the

same bank at the same time, neither access will be valid, and data at the two

specific addresses targeted by the ports within that bank may be corrupted (in

the case that either or both ports are writing) or may result in invalid output (in

the case that both ports are trying to read).

6.42

参数对比

与70V7319S166DD相近的元器件有：70V7319S166DDI、70V7319S133DD、70V7319S133DD8、70V7319S133DDI8、70V7319S133DDI。描述及对比如下：

型号	70V7319S166DD	70V7319S166DDI	70V7319S133DD	70V7319S133DD8	70V7319S133DDI8	70V7319S133DDI
描述	Dual-Port SRAM, 256KX18, 12ns, CMOS, PQFP144, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100	Dual-Port SRAM, 256KX18, 12ns, CMOS, PQFP144, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100	Dual-Port SRAM, 256KX18, 15ns, CMOS, PQFP144, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100	Application Specific SRAM, 256KX18, 15ns, CMOS, PQFP144, 20 X 20 MM, 1.40 MM HEIGHT, TQFP-144	Application Specific SRAM, 256KX18, 15ns, CMOS, PQFP144, 20 X 20 MM, 1.40 MM HEIGHT, TQFP-144	Dual-Port SRAM, 256KX18, 15ns, CMOS, PQFP144, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100
是否Rohs认证	不符合	不符合	不符合	不符合	不符合	不符合
厂商名称	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
包装说明	14 X 14 MM, 1.40 MM HEIGHT, TQFP-100	14 X 14 MM, 1.40 MM HEIGHT, TQFP-100	14 X 14 MM, 1.40 MM HEIGHT, TQFP-100	QFP, QFP144,.87SQ,20	QFP, QFP144,.87SQ,20	14 X 14 MM, 1.40 MM HEIGHT, TQFP-100
Reach Compliance Code	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant
最长访问时间	12 ns	12 ns	15 ns	15 ns	15 ns	15 ns
其他特性	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)	166 MHz	166 MHz	133 MHz	133 MHz	133 MHz	133 MHz
I/O 类型	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 代码	S-PQFP-G144	S-PQFP-G144	S-PQFP-G144	S-PQFP-G144	S-PQFP-G144	S-PQFP-G144
JESD-609代码	e0	e0	e0	e0	e0	e0
内存密度	4718592 bit	4718592 bit	4718592 bit	4718592 bit	4718592 bit	4718592 bit
内存集成电路类型	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	APPLICATION SPECIFIC SRAM	APPLICATION SPECIFIC SRAM	DUAL-PORT SRAM
内存宽度	18	18	18	18	18	18
功能数量	1	1	1	1	1	1
端口数量	2	2	2	2	2	2
端子数量	144	144	144	144	144	144
字数	262144 words	262144 words	262144 words	262144 words	262144 words	262144 words
字数代码	256000	256000	256000	256000	256000	256000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	70 °C	85 °C	70 °C	70 °C	85 °C	85 °C
组织	256KX18	256KX18	256KX18	256KX18	256KX18	256KX18
输出特性	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	LFQFP	LFQFP	LFQFP	QFP	QFP	LFQFP
封装等效代码	QFP144,.87SQ,20	QFP144,.87SQ,20	QFP144,.87SQ,20	QFP144,.87SQ,20	QFP144,.87SQ,20	QFP144,.87SQ,20
封装形状	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
封装形式	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK	FLATPACK	FLATPACK, LOW PROFILE, FINE PITCH
并行/串行	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
电源	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
最大待机电流	0.03 A	0.04 A	0.03 A	0.00003 A	0.00004 A	0.04 A
最小待机电流	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V
最大压摆率	0.79 mA	0.83 mA	0.645 mA	0.645 mA	0.675 mA	0.675 mA
最大供电电压 (Vsup)	3.45 V	3.45 V	3.45 V	3.45 V	3.45 V	3.45 V
最小供电电压 (Vsup)	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V
标称供电电压 (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
表面贴装	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL	INDUSTRIAL	INDUSTRIAL
端子面层	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)	TIN LEAD	TIN LEAD	Tin/Lead (Sn85Pb15)
端子形式	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
端子节距	0.5 mm	0.5 mm	0.5 mm	0.5 mm	0.5 mm	0.5 mm
端子位置	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD
Base Number Matches	1	1	1	1	1	1
零件包装代码	QFP	QFP	QFP	-	-	QFP
针数	144	144	144	-	-	144
ECCN代码	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	-	-	3A991.B.2.A
长度	20 mm	20 mm	20 mm	-	-	20 mm
湿度敏感等级	4	4	4	-	-	4
座面最大高度	1.6 mm	1.6 mm	1.6 mm	-	-	1.6 mm
宽度	20 mm	20 mm	20 mm	-	-	20 mm

gprs接收数据的问题: 我的gprs模块是sim300，使用命令模式建立TCP连接，接收到的数据会直接从串口传给电脑。现在...; hbxt561 嵌入式系统

使用信号的任务间的切换，请给我指出错误: //创建一个信号量 OSSemCreate ((OS_SEM* )&MY_SEM, ...; yefeng115599 实时操作系统RTOS

非线性运算的定点快速实现: 在数值运算中，除基本的加减乘除运算外，还有其它许多非线性运算，如，对数运算，开方运算，指数运算，三角...; Aguilera DSP 与 ARM 处理器

PSoC亮点，一点感慨: 今天没事看了一下PSoC4 Cortex-M0开发板，资源丰富就不用说了！感觉这个开发模式和架构挺...; wuyanyanke 单片机

使用Visual Studio Code创建GD32VF103工程: 在下边网址下载Visual Studio Code https://code.visual...; littleshrimp GD32 MCU

三极管怎么加个反馈: 想100kHz的信号高电压放大，这样用三极管怎么样？但这样输出幅度和三极管的B值有关。能不能...; rockchn 模拟电子

有线电视三大技术指标详解

有线电视三大技术指标详解一个有线电视网络系统性能的好坏，我们通常都用载噪比（C/N）、组合三次差拍比（CTB）、组合二次差拍比（CSO）进行衡量。国家广电行业标准（GY/7 106-1999）规定：有线电视系统的载噪比≥43db、组合三次差拍比≥54db、组合二次差拍比≥54db。那末这三大指标的含义是什么？在这里向大家逐一介绍。一、载噪比定义：在系统的指定点，图象或伴音...[详细]
华硕多款产品选用Atmel maXTouch T系列单芯片控制器

爱特梅尔公司(Atmel Corporation)宣布华硕公司(ASUS)已经选择爱特梅尔最近发布的mXT2952T和mXT1664T控制器，助力多款新型平板电脑和超极本的触摸屏，包括最新推出的 Zenbook Infinity. 两款控制器均为爱特梅尔最新一代maXTouch T 系列的成员。mXT2952T是世界上首个助力15.6英寸触摸屏的超低功率单芯片控制器，而mXT1664T则是业界...[详细]
德州仪器创新日：时刻准备着向创新进发

TI的员工每天都在向创新发起挑战。而近期，TI高性能模拟 (HPA) 部门的接口产品 (INT) 团队将这个挑战提升到了新的层次。这个团队的成员从世界各地飞往达拉斯，通力配合、全身心的投入到全新项目和制造工艺的头脑风暴中。这些团队都做出了实实在在的贡献。来自高速、工业和光学市场产品线的35名员工在达拉斯名为创新日的活动中努力创造出了三十多项发明。而其中的某些产品必将提高技术...[详细]
展讯携手合作伙伴开启国产移动金融安全终端解决方案

集微网消息，展讯通信（以下简称“展讯”），作为中国领先的2G、3G和4G无线通信终端的核心芯片供应商之一，近日在2017展讯全球合作伙伴大会上与北京移动金融产业联盟、中国银联、中国金融电子化公司、北京中清怡和科技有限公司、国美通讯共同开启了国产移动金融安全终端解决方案。智能手机及移动设备的广泛普及已令电子支付无处不在，人们的生活已进入移动支付的时代。在我们享受便捷生活的同时，安全问题不容忽...[详细]
基于STM32单片机的多功能水杯设计

本设计的硬件构成： STM32F103C8T6单片机最小系统板（包含+3.3V稳压电路+时钟晶振电路+复位电路（上电自复位，手动复位）），温度传感器、水位传感器、红外人体传感器、红外反射传感器、超声波测距模块、LCD液晶显示屏、按键、蜂鸣器、LED指示灯、继电器等电路而成；功能介绍： 1、温度传感器采集水温，按键设置水温阈值，人体感应检测人体信号，当发现有人时并且水温低于阈值时，进行加热...[详细]
微鲸与供应商陷款项纠纷，曾效仿乐视模式

3月19日，有供应商向《每日经济新闻》记者透露称，微鲸科技有限公司（以下简称微鲸科技）拖欠了他们2016年7月至2017年8月提供服务的款项。对上述说法，记者很快联系到了微鲸科技方面，对方虽承认有欠款，但否认拖欠款项一说。微鲸科技方面认为，公司不存在拒不执行的行为，目前都处于正常的时间周期里面，毕竟尚未到约定的日期。与此同时，微鲸科技方面还向记者表示，上述供应商是2017年就被公司除...[详细]
联发科获利改善需要时间毛利率40%或成天险

虽然联发科2016年毛利率陡然降低的跌跌不休走势，看似要在2017年上半找到底部后，顺势因产组合比重优化，采用先进制程技术及成本降低方案陆续改善而开始反弹，但公司初估第1季毛利率仍会下探32.5~33.5%的历史新低数字，及第2季毛利率暂时还找不到偏向乐观的理由后，联发科2017年获利增长计划已有向后延宕的压力，甚至40%毛利率大关也越来越有天险的样子，如同变了心的女朋友，一去不回头。在同业间彼...[详细]
关于STM32中AD采样的三种方法分析

　　在进行STM32F中AD采样的学习中，我们知道AD采样的方法有多种，按照逻辑程序处理有三种方式，一种是查询模式，一种是中断处理模式，一种是DMA模式。三种方法按照处理复杂方法DMA模式处理模式效率最高，其次是中断处理模式，最差是查询模式，相信很多学者在学习AD采样程序时，很多例程采用DMA模式，在这里我针对三种程序进行分别分析。　　1、AD采样查询模式　　在AD采样查询模式中，我...[详细]
现代Ioniq的快充曲线与电池接口

现代Ioniq的快充曲线出来了，这台77kWh的电动汽车，确实按照10%到80%18分钟左右的快充功率。在这张图里面，做了一个分解表。 10%-50%的时间为8分35秒 30%-80%的时间为13分46秒备注：这个充电时间受温度的影响还不得而知，目前应该是按照常温来设计的图1 现代Ioniq的快充功率改回原来的版式，可能效果更好点 01、第一部分充电功率和时间...[详细]
中国信通院承接工信部大模型公共服务平台建设工作，联合 360、京东、商汤等

10 月 20 日消息，中国信通院 CAICT 发布消息，2023 年 9 月 25 日，工业和信息化部“2023 年产业技术基础公共服务平台-面向人工智能大模型工程化技术及应用的产业公共服务平台项目”发布中标公示，由中国信息通信研究院（以下简称“中国信通院”）牵头的联合体（参与单位：北京智源人工智能研究院、中国科学院信息工程研究所、三六零科技集团有限公司、上海商汤科技开发有限公司、京东科技信息...[详细]
e 络盟推出德州仪器参考设计，以简化 Xilinx MPSoC、SoC 和 FPGA

中国上海，2018年5月9日—全球电子元器件与开发服务分销商e 络盟推出两款德州仪器参考设计，为Xilinx® Zynq® UltraScale+™MPSoC系列产品的客户提供支持，让他们可以更轻松地运用这些设备开发电源解决方案，加速其创新应用开发。这些参考设计为可扩展电源，可为基于 FPGA 的 Xilinx Zynq UltraScale+ 系列MPSoC器件供电。有了它们，客户在完全...[详细]
STM8单片机的中断控制和中断功能

内部中断：一般是由硬件错误或者运算过程中出错引起的，一般是不可避免的; 外部中断：是处理器的外设发出的中断请求，如定时器中断，UART 接收中断，外部中断一般都可以通过中断控制器进行屏蔽; 1.ITC 功能概述： ……所有 IO 引脚都具有外部中断能力，每个端口都有独立的中断向量以及独立的标志;外设中断能力; ……软件中断能力(TRAP) ……具有灵活的优先级和中断等级管理，支持可嵌...[详细]
智能照明系统室内环境光采集电路图

　　系统采用单片机为控制器，用热释人体红外传感器和光照强度传感系统来检测室内有无人员及室内光强，提出了一个智能照明控制系统的原理框图，并在此基础上设计了智能照明控制系统的部分硬件电路，该系统采用模块化结构设计，条理清晰，便于改进和扩充。同时还具有体积小，控制方便，可靠性高等优点，可以满足办公场所智能照明控制的要求，以达到节能目的。　　室内环境光采集电路　　室内环境光采集电路如图2所示。工作原...[详细]
TE Connectivity 推出SFP28和QSFP28电缆组件

TE Connectivity（TE）凭借着信号完整性专业知识，可以提供市面上性能最高的25 Gbps SFP28和QSFP28电缆组件产品组合。TE的电缆组件支持的聚合数据传输率为100 Gbps和200 Gbps，TE不仅提供这些25 Gbps电缆组件，还提供匹配的连接器和笼，因此可为数据通信应用提供一站式的完整解决方案。 TE SFP28和QSFP28电缆组件的优势在于支持的聚合数据传输...[详细]
保时捷Panamera S混动车4种驱动模式解读

保时捷Panamera S E-Hybrid插电式混动车经过超过42项驾驶测试以及1,200公里的测试里程后，其最新的综合燃效数据为53.4英里/加仑（油耗4.4升/百公里），二氧化碳排量为71克/公里，电量消耗为162瓦时/公里。纯电动模式下，该车行驶里程为36公里。其动力总成包括一台符合欧6排放标准的3.0升V6发动机（最大功率245千瓦，峰值扭矩440牛米）以及一台峰值扭矩达到...[详细]