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HIGH-SPEED 3.3V 256K x 18

SYNCHRONOUS

BANK-SWITCHABLE

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

Features:

◆

70V7319S

◆

256K x 18 Synchronous Bank-Switchable Dual-ported SRAM

Architecture

–

64 independent 4K x 18 banks

– 4 megabits of memory on chip

Bank access controlled via bank address pins

High-speed data access

– Commercial: 3.4ns (200MHz)/3.6ns (166MHz)/

4.2ns (133MHz) (max.)

– Industrial: 4.2ns (133MHz) (max.)

Selectable Pipelined or Flow-Through output mode

Counter enable and repeat features

Dual chip enables allow for depth expansion without

additional logic

Full synchronous operation on both ports

– 5ns cycle time, 200MHz operation (14Gbps bandwidth)

– Fast 3.4ns clock to data out

◆

– 1.5ns setup to clock and 0.5ns hold on all control, data, and

address inputs @ 200MH

– Data input, address, byte enable and control registers

– Self-timed write allows fast cycle time

Separate byte controls for multiplexed bus and bus match-

ing compatibility

LVTTL- compatible, 3.3V (±150mV) power supply

for core

LVTTL compatible, selectable 3.3V (±150mV) or 2.5V

(±100mV) power supply for I/Os and control signals on each

port

Industrial temperature range (-40°C to +85°C) is

available at 133MHz

Available in a 208-pin fine pitch Ball Grid Array (fpBGA) and

256-pin Ball Grid Array (BGA)

Supports JTAG features compliant with IEEE 1149.1

Green parts available, see ordering information

Functional Block Diagram

PL/FT

OPT

CLK

ADS

CNTEN

REPEAT

R/W

PL/FT

OPT

CLK

ADS

CNTEN

REPEAT

R/W

CONTROL

LOGIC

MUX

4Kx18

MEMORY

ARRAY

(BANK 0)

MUX

CONTROL

LOGIC

I/O

0L-17L

I/O

CONTROL

MUX

4Kx18

MEMORY

ARRAY

(BANK 1)

MUX

I/O

CONTROL

I/O

0R-17R

11L

ADDRESS

DECODE

ADDRESS

DECODE

11R

BANK

DECODE

MUX

4Kx18

MEMORY

ARRAY

(BANK 63)

BANK

DECODE

NOTE:

1. The Bank-Switchable dual-port uses a true SRAM core

instead of the traditional dual-port SRAM core. As a result, it

has unique operating characteristics. Please refer to the

functional description on page 19 for details.

MUX

TDI

TDO

JTAG

TMS

TCK

TRST

5629 drw 01

OCTOBER 2019

DSC 5629/13

70V7319S

High-Speed 256K x 18 Synchronous Bank-Switchable Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Description:

The IDT70V7319 is a high-speed 256Kx18 (4Mbit) synchronous

Bank-Switchable Dual-Ported SRAM organized into 64 independent

4Kx18 banks. The device has two independent ports with separate

control, address, and I/O pins for each port, allowing each port to access

any 4Kx18 memory block not already accessed by the other port.

Accesses by the ports into specific banks are controlled via the bank

address pins under the user's direct control.

Registers on control, data, and address inputs provide minimal setup

and hold times. The timing latitude provided by this approach allows

systems to be designed with very short cycle times. With an input data

unidirectional or bidirectional data flow in bursts. An automatic power

down feature, controlled by CE

and CE

, permits the on-chip circuitry of

each port to enter a very low standby power mode. The dual chip enables

also facilitate depth expansion.

The 70V7319 can support an operating voltage of either 3.3V or 2.5V

on one or both ports, controllable by the OPT pins. The power supply for

the core of the device(V

) remains at 3.3V. Please refer also to the

functional description on page 18.

Pin Configuration

(1,2,3,4)

A10

A11

A12

A13

A14

A15

A16

A17

TDO

B10

CLK

CNTEN

B11

B12

B13

B14

OPT

B15

B16

B17

TDI

C10

ADS

C11

C12

C13

DDQR

I/O

C14

C15

C16

C17

DDQL

I/O

DDQR

PL/FT

10L

D10

R/W

D11

D12

D13

D14

I/O

D15

D16

D17

I/O

10L

11L

REPEAT

E14

DDQL

I/O

E15

E16

I/O

E17

I/O

11L

NC V

DDQR

I/O

10R

I/O

F14

F15

F16

F17

DDQL

I/O

11R

G14

I/O

G15

G16

DDQR

G17

I/O

12L

NC V

DDQL

I/O

H17

DDQR

I/O

12R

70V7319

BF208

(5)

208-Pin fpBGA

Top View

(6)

H14

H15

H16

J14

J15

J16

I/O

J17

DDQL

K14

K15

DDQR

K16

K17

I/O

14R

I/O

13R

I/O

L14

DDQL

I/O

L15

L16

L17

I/O

14L

DDQR

I/O

13L

M14

I/O

M15

M16

I/O

M17

DDQL

I/O

15R

N14

N15

I/O

DDQR

N16

N17

I/O

15L

P10

P11

P12

P13

I/O

DDQL

P14

P15

P16

I/O

P17

I/O

16R

I/O

16L

DDQR

TRST

R10

CLK

CNTEN

R11

R12

R13

R14

I/O

R15

R16

R17

I/O

17R

TCK BA

T10

ADS

T11

T12

T13

T14

DDQL

I/O

DDQR

T15

T16

T17

I/O

17L

DDQL

TMS

10R

U10

R/W

U11

U12

U13

U14

U15

U16

U17

NC PL/FT

11R

REPEAT

OPT

I/O

NOTES:

1. All V

pins must be connected to 3.3V power supply.

2. All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

(3.3V), and 2.5V if OPT pin for that port is

set to V

(0V).

3. All V

pins must be connected to ground supply.

4. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.

5. This package code is used to reference the package diagram.

6. This text does not indicate orientation of the actual part-marking.

5629 drw 02c

6.42

70V7319S

High-Speed 256K x 18 Synchronous Bank-Switchable Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Pin Configuration

(1,2,3,4)

(con't.)

70V7319

BC256

(5)

256-Pin BGA

Top View

(6)

A10

A11

A12

A13

A14

A15

A16

TDI

11L

CNTEN

B10

B11

B12

B13

B14

B15

B16

TDO

R/W

REPEAT

C10

C11

C12

C13

C14

C15

C16

I/O

10L

CLK

ADS

D10

D11

D12

D13

OPT

D14

D15

I/O

D16

I/O

PL/

DDQL

DDQR

DDQL

DDQR

E10

E11

E12

E13

E14

E15

I/O

E16

I/O

10R

I/O

10L

DDQL

F10

F11

DDQR

F12

F13

F14

I/O

F15

F16

I/O

11L

I/O

11R

DDQL

G10

G11

DDQR

I/O

G12

G13

G14

G15

I/O

G16

I/O

12L

DDQR

H10

H11

H12

DDQL

I/O

H13

H14

H15

H16

I/O

12R

DDQR

J10

J11

J12

DDQL

J13

J14

J15

I/O

J16

I/O

13L

I/O

14R

I/O

13R

DDQL

K10

K11

DDQR

I/O

K12

K13

K14

K15

K16

I/O

14L

DDQL

L10

L11

L12

DDQR

L13

L14

L15

I/O

L16

I/O

15L

I/O

15R

DDQR

M10

M11

M12

DDQL

I/O

M13

M14

M15

I/O

M16

I/O

16R

I/O

16L

DDQR

N10

N11

N12

DDQL

I/O

N13

N14

N15

N16

I/O

17R

PL/

DDQR

DDQL

DDQR

DDQL

P10

P11

P12

P13

P14

I/O

P15

P16

I/O

17L

TMS

10R

CLK

ADS

R10

R11

R12

R13

R14

R15

I/O

R16

TRST

R/W

REPEAT

T10

T11

T12

T13

OPT

T14

T15

T16

TCK

11R

CNTEN

5629 drw 02d

NOTES:

1. All V

pins must be connected to 3.3V power supply.

2. All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

(3.3V), and 2.5V if OPT pin for that port is

set to V

(0V).

3. All V

pins must be connected to ground supply.

4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.

5. This package code is used to reference the package diagram.

6. This text does not indicate orientation of the actual part-marking.

6.42

70V7319S

High-Speed 256K x 18 Synchronous Bank-Switchable Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Pin Names

Left Port

R/W

- BA

- A

11L

I/O

- I/O

17L

CLK

PL/FT

ADS

CNTEN

REPEAT

DDQL

OPT

TDI

TDO

TCK

TMS

TRST

Right Port

R/W

- BA

- A

11R

I/O

- I/O

17R

CLK

PL/FT

ADS

CNTEN

REPEAT

DDQR

OPT

Chip Enables

Read/Write Enable

Output Enable

Bank Address

(4)

Address

Data Input/Output

Clock

Pipeline/Flow-Through

Address Strobe Enable

Counter Enable

Counter Repeat

(3)

Byte Enables (9-bit bytes)

Power (I/O Bus) (3.3V or 2.5V)

(1)

Option for selecting V

DDQX

(1,2)

Power (3.3V)

(1)

Ground (0V)

Test Data Input

Test Data Output

Test Logic Clock (10MHz)

Test Mode Select

Reset (Initialize TAP Controller)

5629 tbl 01

Names

NOTES:

1. V

, OPT

, and V

DDQX

must be set to appropriate operating levels prior to applying inputs

on the I/Os and controls for that port.

2. OPT

selects the operating voltage levels for the I/Os and controls on that port. If OPT

set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V levels and V

DDQX

must

be supplied at 3.3V. If OPT

is set to VIL (0V), then that port's I/Os and address controls will

operate at 2.5V levels and V

DDQX

must be supplied at 2.5V. The OPT pins are independent

of one another—both ports can operate at 3.3V levels, both can operate at 2.5V levels, or either

can operate at 3.3V with the other at 2.5V.

3. When

REPEAT

is asserted, the counter will reset to the last valid address loaded via

ADS

4. Accesses by the ports into specific banks are controlled by the bank address pins under

the user's direct control: each port can access any bank of memory with the shared array

that is not currently being accessed by the opposite port (i.e., BA

- BA

≠

- BA

In the event that both ports try to access the same bank at the same time, neither access

will be valid, and data at the two specific addresses targeted by the ports within that bank may

be corrupted (in the case that either or both ports are writing) or may result in invalid output

(in the case that both ports are trying to read).

6.42

70V7319S

High-Speed 256K x 18 Synchronous Bank-Switchable Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Truth Table I—Read/Write and Enable Control

(1,2,3,4)

CLK

↑

R/W

Upper Byte

I/O

9-17

High-Z

OUT

High-Z

Lower Byte

I/O

0-8

High-Z

OUT

High-Z

OUT

High-Z

MODE

Deselected–Power Down

All Bytes Deselected

Write to Lower Byte Only

Write to Upper Byte Only

Write to both Bytes

Read Lower Byte Only

Read UpperByte Only

Read both Bytes

Outputs Disabled

5629 tbl 02

NOTES:

1. "H" = V

IH,

"L" = V

IL,

"X" = Don't Care.

ADS, CNTEN, REPEAT

are set as appropriate for address access. Refer to Truth Table II for details.

is an asynchronous input signal.

4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.

Truth Table II—Address and Address Counter Control

(1,2,7)

Address

An + 1

Addr

Used

An + 1

CLK

↑

ADS

(4)

CNTEN

(5)

REPEAT

(6)

(4)

I/O

(3)

I/O

(n)

I/O

(n+1)

I/O

(n+1)

I/O

(0)

External Address Used

Counter Enabled—Internal Address generation

External Address Blocked—Counter disabled (An + 1 reused)

Counter Set to last valid

ADS

load

5629 tbl 03

MODE

NOTES:

1. "H" = V

IH,

"L" = V

IL,

"X" = Don't Care.

2. Read and write operations are controlled by the appropriate setting of R/W,

, CE

UB/LB

and

OE.

3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.

ADS

and

REPEAT

are independent of all other memory control signals including

, CE

and

UB/LB

5. The address counter advances if

CNTEN

= V

on the rising edge of CLK, regardless of all other memory control signals including

, CE

UB/LB.

6. When

REPEAT

is asserted, the counter will reset to the last valid address loaded via

ADS.

This value is not set at power-up: a known location should be loaded via

ADS

during initialization

if desired. Any subsequent

ADS

access during operations will update the

REPEAT

address location.

7. The counter includes bank address and internal address. The counter will advance across bank boundaries. For example, if the counter is in Bank 0, at address FFFh, and is advanced one

location, it will move to address 0h in Bank 1. By the same token, the counter at FFFh in Bank 63 will advance to 0h in Bank 0. Refer to Timing Waveform of Counter Repeat, page 17. Care

should be taken during operation to avoid having both counters point to the same bank (i.e., ensure BA

- BA

≠

- BA

), as this condition will invalidate the access for both ports.

Please refer to the functional description on page 18 for details.

6.42