HIGH-SPEED 3.3V 32K x 9
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
Features:
◆
◆
70V9179L
◆
◆
◆
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 7.5ns (max.)
Low-power operation
– IDT70V9179L
Active: 500mW (typ.)
Standby: 1.5mW (typ.)
Flow-Through or Pipelined output mode on either port via
the
FT/PIPE
pins
Dual chip enables allow for depth expansion without
additional logic
◆
◆
◆
◆
◆
Counter enable and reset features
Full synchronous operation on both ports
– 4ns setup to clock and 0ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 7.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 12ns cycle time, 83MHz operation in Pipelined output mode
LVTTL- compatible, single 3.3V (±0.3V) power supply
Available in a 100-pin Thin Quad Flatpack (TQFP)
Green parts available, see ordering information
Functional Block Diagram
R/W
L
OE
L
CE
0L
CE
1L
R/W
R
OE
R
CE
0R
CE
1R
1
0
0/1
1
0
0/1
FT/PIPE
L
0/1
1
0
0
1
0/1
FT/PIPE
R
,
I/O
0L
- I/O
8L
I/O
Control
I/O
Control
I/O
0R
- I/O
8R
A
14L
A
0L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
A
14R
A
0R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
4860 drw 01
1
Feb.18.20
70V9179L
High-Speed 32K x 9 Dual-Port Synchronous Pipelined Static RAM
Industrial and
Commercial Temperature Range
Description:
The IDT70V9179 is a high-speed 64/32K x 9 bit synchronous Dual
Port RAM. The memory array utilizes Dual-Port memory cells to allow
simultaneous access of any address from both ports. Registers on control,
data, and address inputs provide minimal setup and hold times. The timing
latitude provided by this approach allows systems to be designed with very
short cycle times.
With an input data register, the IDT70V9179 has been optimized for
applications having unidirectional or bidirectional data flow in bursts. An
automatic power down feature, controlled by
CE
0
and CE
1,
permits the
on-chip circuitry of each port to enter a very low standby power mode.
Fabricated using CMOS high-performance technology, these devices
typically operate on only 500mW of power.
Pin Configuration
(1,2,3)
NC
NC
A
7R
A
8R
A
9R
A
10R
A
11R
A
12R
A
13R
A
14R
NC
NC
Vss
NC
NC
NC
NC
CE
0R
CE
1R
CNTRST
R
R/W
R
OE
R
FT/PIPE
R
Vss
NC
NC
A
6R
A
5R
A
4R
A
3R
A
2R
A
1R
A
0R
CNTEN
R
CLK
R
ADS
R
Vss
Vss
ADS
L
CLK
L
CNTEN
L
A
0L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
NC
NC
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
76
49
77
48
78
79
47
46
80
45
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1 2 3 4 5 6 7 8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
70V9179
PNG100
(4)
100-Pin TQFP
Top View
NC
NC
I/O
8R
I/O
7R
I/O
6R
I/O
5R
I/O
4R
I/O
3R
V
DD
I/O
2R
I/O
1R
I/O
0R
Vss
V
DD
I/O
0L
I/O
1L
Vss
I/O
2L
I/O
3L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
I/O
8L
Vss
NC
NC
A
7L
A
8L
A
9L
A
10L
A
11L
A
12L
A
13L
A
14L
NC
NC
V
DD
NC
NC
NC
NC
CE
0L
CE
1L
CNTRST
L
R/W
L
OE
L
FT/PIPE
L
NC
NC
4860 drw 02
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
6.42
2
Feb.18.20
70V9179L
High-Speed 32K x 9 Dual-Port Synchronous Pipelined Static RAM
Industrial and
Commercial Temperature Range
Pin Names
Left Port
CE
0L,
CE
1L
R/W
L
OE
L
A
0L
- A
14L
I/O
0L
- I/O
8L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
FT/PIPE
L
Right Port
CE
0R,
CE
1R
R/W
R
OE
R
A
0R
- A
14R
I/O
0R
- I/O
8R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
FT/PIPE
R
V
DD
V
SS
Names
Chip Enables
Read/Write Enable
Output Enable
Address
Data Input/Output
Clock
Address Strobe Enable
Counter Enable
Counter Reset
Flow-Through / Pipeline
Power (3.3V)
Ground (0V)
4860 tbl 01
NOTE:
1.
LB
and
UB
are single buffered regardless of state of
FT/PIPE.
2.
CEo
and CE
1
are single buffered when
FT/PIPE
= V
IL
,
CEo
and CE
1
are double buffered when
FT/PIPE
= V
IH
,
i.e. the signals take two cycles to deselect.
Truth Table I—Read/Write and Enable Control
(1,2,3)
OE
X
X
X
L
H
CLK
↑
↑
↑
↑
X
CE
0
H
X
L
L
L
CE
1
X
L
H
H
H
R/W
X
X
L
H
X
I/O
0-8
High-Z
High-Z
DATA
IN
DATA
OUT
High-Z
Deselected–Power Down
Deselected–Power Down
Write
Read
Outputs Disabled
4860 tbl 02
MODE
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2.
ADS, CNTEN, CNTRST
= X.
3.
OE
is an asynchronous input signal.
Truth Table II—Address Counter Control
(1,2,3)
External
Address
An
X
X
X
Previous
Internal
Address
X
An
An + 1
X
Internal
Address
Used
An
An + 1
An + 1
A
0
CLK
↑
↑
↑
↑
ADS
L
(4)
H
H
X
CNTEN
X
L
(5)
H
X
CNTRST
H
H
H
L
(4)
I/O
(3)
D
I/O
(n)
D
I/O
(n+1)
D
I/O
(n+1)
D
I/O
(0)
External Address Used
Counter Enabled—Internal Address generation
External Address Blocked—Counter disabled (An + 1 reused)
Counter Reset to Address 0
4860 tbl 03
MODE
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2.
CE
0
and
OE
= V
IL
; CE
1
and R/W = V
IH
.
3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle.
4.
ADS
and
CNTRST
are independent of all other signals including
CE
0
and CE
1
.
5. The address counter advances if
CNTEN
= V
IL
on the rising edge of CLK, regardless of all other signals including
CE
0
and CE
1
.
6.42
3
Feb.18.20
70V9179L
High-Speed 32K x 9 Dual-Port Synchronous Pipelined Static RAM
Industrial and
Commercial Temperature Range
Recommended Operating
Temperature and Supply Voltage
Grade
Commercial
Industrial
Ambient
Temperature
(2)
0
O
C to +70
O
C
-40
O
C to +85
O
C
GND
0V
0V
V
DD
3.3V
+
0.3V
3.3V
+
0.3V
4860 tbl 04
Recommended DC Operating
Conditions
Symbol
V
DD
V
SS
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
3.0
0
2.0V
-0.3
(1)
Typ.
3.3
0
____
____
Max.
3.6
0
V
CC
+0.3V
(2)
0.8
Unit
V
V
V
V
4860 tbl 05
NOTES:
1. This is the parameter T
A
. This is the "instant on" case temperature.
NOTES:
1. V
IL
> -1.5V for pulse width less than 10 ns.
2. V
TERM
must not exceed V
DD
+0.3V.
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
Capacitance
(1)
Unit
V
Rating
Terminal Voltage
with Respect to
GND
Temperature
Under Bias
Storage
Temperature
Junction
Temperature
DC Output Current
Commercial
& Industrial
-0.5 to +4.6
(T
A
= +25°C, f = 1.0MH
Z
)
Symbol
C
IN
C
OUT
(3)
Parameter
Input Capacitance
Output Capacitance
Conditions
(2)
V
IN
= 3dV
V
OUT
= 3dV
Max.
9
10
Unit
pF
pF
4860 tbl 07
T
BIAS
T
STG
T
JN
I
OUT
-55 to +125
-65 to +150
+150
50
o
C
C
C
o
o
mA
4860 tbl 06
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. C
OUT
also references C
I/O
.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
TERM
must not exceed V
DD
+0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> V
DD
+ 0.3V.
3. Ambient Temperature Under DC Bias. NO AC Conditions. Chip Deselected.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(V
DD
= 3.3V ± 0.3V)
70V9179L
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
(1)
Output Leakage Current
Output Low Voltage
Output High Voltage
V
DD
= 3.6V, V
IN
= 0V to V
DD
CE
= V
IH
or CE
1
= V
IL
, V
OUT
= 0V to V
DD
I
OL
= +4mA
I
OH
= -4mA
Test Conditions
Min.
___
___
___
Max.
5
5
0.4
___
Unit
µA
µA
V
V
2.4
NOTE:
1. At V
DD
< 2.0V input leakages are undefined.
4860 tbl 08_79
6.42
4
Feb.18.20
70V9179L
High-Speed 32K x 9 Dual-Port Synchronous Pipelined Static RAM
Industrial and
Commercial Temperature Range
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range
(3)
(V
DD
= 3.3V ± 0.3V)
70V9179L7
Com'l Only
Symbol
I
CC
Parameter
Dynamic Operating
Current (Both
Ports Active)
Standby Current
(Both Ports - TTL
Level Inputs)
Standby
Current (One
Port - TTL
Level Inputs)
Full Standby
Current (Both
Ports - CMOS
Level Inputs)
Full Standby
Current (One
Port - CMOS
Level Inputs)
Test Condition
CE
L
and
CE
R
= V
IL
,
Outputs Disabled,
f = f
MAX
(1)
CE
L
=
CE
R
= V
IH
f = f
MAX
(1)
CE
"A"
= V
IL
and
CE
"B"
= V
IH
(5)
Active Port Outputs
Disabled, f=f
MAX
(1)
Both Ports
CE
L
and
CE
R
> V
DD
- 0.2V,
V
IN
> V
DD
- 0.2V or
V
IN
< 0.2V, f = 0
(2)
Version
COM'L
IND
COM'L
IND
COM'L
IND
COM'L
IND
L
L
L
L
L
L
L
L
L
L
Typ.
(4)
200
____
70V9179L9
Com'l & Ind
Typ.
(4)
180
180
50
50
110
110
0.4
0.4
100
100
Max.
260
280
100
120
190
205
3
6
180
195
70V9179L12
Com'l Only
Typ.
(4)
150
____
Max.
310
____
Max.
230
____
Unit
mA
I
SB1
65
____
130
____
40
____
80
____
mA
I
SB2
140
____
245
____
100
____
175
____
mA
I
SB3
0.4
____
3
____
0.4
____
3
____
mA
I
SB4
CE
"A"
< 0.2V and
COM'L
CE
"B"
> V
DD
- 0.2V
(5)
V
IN
> V
DD
- 0.2V or
V
IN
< 0.2V, Active Port,
IND
Outputs Disabled, f = f
MAX
(1)
130
____
235
____
90
____
165
____
mA
NOTES:
1. At f = f
MAX
, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/t
CYC
, using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. V
DD
= 3.3V, T
A
= 25°C for Typ, and are not production tested. I
CC DC
(f=0) = 90mA (Typ).
5.
CE
X
= V
IL
means
CE
0X
= V
IL
and CE
1X
= V
IH
CE
X
= V
IH
means
CE
0X
= V
IH
or CE
1X
= V
IL
CE
X
< 0.2V means
CE
0X
< 0.2V and CE
1X
> V
CC
- 0.2V
CE
X
> V
DD
- 0.2V means
CE
0X
> V
DD
- 0.2V or CE
1X
< 0.2V
"X" represents "L" for left port or "R" for right port.
4860 tbl 09_79
6.42
5
Feb.18.20
