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71V428YFS12YI

Standard SRAM, 1MX4, 12ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, SOJ-32

器件类别:存储    存储   

厂商名称:IDT (Integrated Device Technology)

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器件参数
参数名称
属性值
是否无铅
含铅
是否Rohs认证
不符合
厂商名称
IDT (Integrated Device Technology)
包装说明
SOJ, SOJ32,.44
Reach Compliance Code
not_compliant
ECCN代码
3A991.B.2.A
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3.3V CMOS Static RAM
4 Meg (1M x 4-Bit)
IDT71V428S
IDT71V428L
x
x
x
Features
1M x 4 advanced high-speed CMOS Static RAM
JEDEC Center Power / GND pinout for reduced noise
Equal access and cycle times
— Commercial and Industrial: 10/12/15ns
Single 3.3V power supply
One Chip Select plus one Output Enable pin
Bidirectional data inputs and outputs directly
LVTTL-compatible
Low power consumption via chip deselect
Available in 32-pin, 400 mil plastic SOJ package.
Description
The IDT71V428 is a 4,194,304-bit high-speed Static RAM orga-
nized as 1M x 4. It is fabricated using IDT’s high-perfomance, high-
reliability CMOS technology. This state-of-the-art technology, com-
bined with innovative circuit design techniques, provides a cost-
effective solution for high-speed memory needs.
The IDT71V428 has an output enable pin which operates as fast as
5ns, with address access times as fast as 10ns. All bidirectional inputs
and outputs of the IDT71V428 are LVTTL-compatible and operation is
from a single 3.3V supply. Fully static asynchronous circuitry is used,
requiring no clocks or refresh for operation.
The IDT71V428 is packaged in a 32-pin, 400 mil Plastic SOJ.
x
x
x
x
x
Functional Block Diagram
A
0
A
19
ADDRESS
DECODER
4,194,304-BIT
MEMORY ARRAY
I/O
0
– I/O
3
4
I/O CONTROL
4
4
WE
OE
CS
CONTROL
LOGIC
3623 drw 01
NOVEMBER 2002
1
©2002 Integrated Device Technology, Inc.
DSC-3623/04
IDT71V428S, IDT71V428L, 3.3V CMOS Static RAM
4 Meg (1M x 4-Bit)
Commercial and Industrial Temperature Ranges
Pin Configuration
A
0
A
1
A
2
A
3
A
4
CS
I/O
0
V
DD
V
SS
I/O
1
WE
A
5
A
6
A
7
A
8
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
19
A
18
A
17
A
16
A
15
OE
I/O
3
V
SS
V
DD
I/O
2
A
14
A
13
A
12
A
11
A
10
NC
Pin Description
A
0
– A
19
CS
WE
OE
I/O
0
- I/O
3
V
DD
V
SS
Address Inputs
Chip Select
Write Enable
Output Enable
Data Input/Output
3.3V Power
Ground
Input
Input
Input
Input
I/O
Power
Gnd
3623 tbl 02
SO32-3
Capacitance
(T
A
= +25°C, f = 1.0MHz, SOJ package)
Symbol
C
IN
C
I/O
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
7
8
Unit
pF
pF
3623 tbl 03
SOJ
Top View
3623 drw 02
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
Truth Table
(1,2)
CS
L
L
L
H
V
HC
(3)
OE
L
X
H
X
X
WE
H
L
H
X
X
I/O
DATA
OUT
DATA
IN
High-Z
High-Z
High-Z
Function
Read Data
Write Data
Output Disabled
Deselected - Standby (I
SB
)
Deselected - Standby (I
SB1
)
3623 tbl 01
NOTES:
1. H = V
IH
, L = V
IL
, x = Don't care.
2. V
LC
= 0.2V, V
HC
= V
CC
-0.2V.
3. Other inputs
≥V
HC
or
≤V
LC
.
6.42
2
IDT71V428S, IDT71V428L, 3.3V CMOS Static RAM
4 Meg (1M x 4-Bit)
Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings
(1)
Symbol
V
DD
V
IN
, V
OUT
T
BIAS
T
STG
P
T
I
OUT
Rating
Supply Voltage Relative to
V
SS
Terminal Voltage Relative
to V
SS
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
-0.5 to +4.6
-0.5 to V
DD
+0.5
-55 to +125
-55 to +125
1
50
Unit
V
V
o
o
Recommended Operating
Temperature and Supply Voltage
Grade
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
V
SS
0V
0V
V
DD
See Below
See Below
3623 tbl 05
C
C
W
mA
3623 tbl 04
Recommended DC Operating
Conditions
Symbol
V
DD
V
SS
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
3.0
0
2.0
-0.3
(2)
Typ.
3.3
0
____
____
Max.
3.6
0
V
DD
+0.3
(1)
0.8
Unit
V
V
V
V
3623 tbl 06
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
NOTES:
1. V
IH
(max.) = V
DD
+2V for pulse width less than 5ns, once per cycle.
2. V
IL
(min.) = –2V for pulse width less than 5ns, once per cycle.
DC Electrical Characteristics
(V
DD
= Min. to Max., Commercial and Industrial Temperature Ranges)
IDT71V428
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Condition
V
DD
= Max., V
IN
= V
SS
to V
DD
V
DD
= Max.,
CS
= V
IH
, V
OUT
= V
SS
to V
DD
I
OL
= 8mA, V
DD
= Min.
I
OH
= -4mA, V
DD
= Min.
Min.
___
___
___
Max.
5
5
0.4
___
Unit
µA
µA
V
V
3623 tbl 07
2.4
DC Electrical Characteristics
(1,2,3)
(V
DD
= Min. to Max., V
LC
= 0.2V, V
HC
= V
DD
– 0.2V)
71V428S/L10
Symbol
I
CC
Parameter
Dynam ic Operating Current
CS
V
LC
, Outputs Open, V
DD
= Max., f = f
MAX
(4)
Dynamic Standby Power Supply Current
CS
V
HC
, Outputs Open, V
DD
= Max., f = f
MAX
(4)
Full Standby Power Supply Current (static)
CS
V
HC
, Outputs Open, V
DD
= Max., f = 0
(4)
S
L
S
L
S
L
Com'l.
150
140
60
40
20
10
Ind.
(5)
150
60
20
71V428S/L12
Com'l.
140
130
50
35
20
10
Ind.
140
130
50
35
20
10
71V428S/L15
Com'l.
130
120
40
30
20
10
Ind.
130
120
40
30
20
10
Unit
mA
mA
mA
mA
mA
mA
3623 tbl 08
I
SB
I
SB1
NOTES:
1. All values are maximum guaranteed values.
2. All inputs switch between 0.2V (Low) and V
DD
- 0.2V (High).
3. Power specifications are preliminary.
4. f
MAX
= 1/t
RC
(all address inputs are cycling at f
MAX
); f = 0 means no address input lines are changing.
5. Standard power 10ns (S10) speed grade only.
6.42
3
IDT71V428S, IDT71V428L, 3.3V CMOS Static RAM
4 Meg (1M x 4-Bit)
Commercial and Industrial Temperature Ranges
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
1.5ns
1.5V
1.5V
See Figure 1, 2 and 3
3623 tbl 09
AC Test Loads
3.3V
+1.5V
50Ω
I/O
Z
0
= 50Ω
30pF
3623 drw 03
3623 drw 04
320Ω
DATA
OUT
5pF*
350Ω
Figure 1. AC Test Load
* Including jig and scope capacitance.
Figure 2. AC Test Load
(for t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
OW,
and t
WHZ
)
7
6
∆t
AA,
t
ACS
(Typical, ns) 5
4
3
2
1
8 20 40 60 80 100 120 140 160 180 200
CAPACITANCE (pF)
Figure 3. Output Capacitive Derating
3623 drw 05
6.42
4
IDT71V428S, IDT71V428L, 3.3V CMOS Static RAM
4 Meg (1M x 4-Bit)
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
Symbol
READ CYCLE
t
RC
t
AA
t
ACS
t
CLZ
(1)
t
CHZ
(1)
t
OE
t
OLZ
(1)
t
OHZ
(1)
t
OH
t
PU
(1)
t
PD
(1)
WRITE CYCLE
t
WC
t
AW
t
CW
t
AS
t
WP
t
WR
t
DW
t
DH
t
OW
(1)
t
WHZ
(1)
Write Cycle Time
Address Valid to End of Write
Chip Select to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data Valid to End of Write
Data Hold Time
Output Active from End of Write
Write Enable to Output in High-Z
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select to Output in Low-Z
Chip Deselect to Output in High-Z
Output Enable to Output Valid
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
Output Hold from Address Change
Chip Select to Power Up Time
Chip Deselect to Power Down Time
Parameter
(V
DD
= 3.3V ± 10%, Commercial and Industrial Temperature Ranges)
71V428S/L10
(2)
Min.
Max.
71V428S/L12
Min.
Max.
71V428S/L15
Min.
Max.
Unit
10
____
____
____
12
____
____
____
15
____
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
____
12
12
____
15
15
____
4
____
4
____
4
____
5
5
____
6
6
____
7
7
____
____
____
____
0
____
0
____
0
____
5
____
6
____
7
____
4
0
____
4
0
____
4
0
____
____
____
____
10
12
15
10
8
8
0
8
0
6
0
3
____
____
____
____
____
____
____
____
____
12
8
8
0
8
0
6
0
3
____
____
____
____
____
____
____
____
____
15
10
10
0
10
0
7
0
3
____
____
____
____
____
____
____
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3623 tbl 10
____
____
____
6
7
7
NOTES:
1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.
2. 0°C to +70°C temperature range only for low power 10ns (L10) speed grade.
6.42
5
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