128K x 36 memory configuration, flow-through outputs
Supports high performance system speed - 95 MHz
(8ns Clock-to-Data Access)
ZBT
TM
Feature - No dead cycles between write and read
cycles
Internally synchronized signal eliminates the need to
control
OE
Single R/W (READ/WRITE) control pin
4-word burst capability (Interleaved or linear)
Individual byte write (BW
1
-
BW
4
) control (May tie active)
Three chip enables for simple depth expansion
Single 3.3V power supply (±5%)
Packaged in a JEDEC standard 100-pin TQFP package
Description
The IDT71V547 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)
synchronous SRAM organized as 128K x 36 bits. It is designed to eliminate
dead bus cycles when turning the bus around between reads and writes,
or writes and reads. Thus it has been given the name ZBT
TM
, or Zero Bus
Turn-around.
Address and control signals are applied to the SRAM during one clock
cycle, and on the next clock cycle, its associated data cycle occurs, be it
read or write.
The IDT71V547 contains address, data-in and control signal registers.
The outputs are flow-through (no output data register). Output enable is
the only asynchronous signal and can be used to disable the outputs at
any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V547 to
be suspended as long as necessary. All synchronous inputs are
ignored when
CEN
is high and the internal device registers will hold
their previous values.
There are three chip enable pins (CE
1
, CE
2
,
CE
2
) that allow the user
to deselect the device when desired. If any one of these three is not active
when ADV/LD is low, no new memory operation can be initiated and any
burst in progress is stopped. However, any pending data transfers (reads
or writes) will be completed. The data bus will tri-state one cycle after the
chip was deselected or write initiated.
The IDT71V547 has an on-chip burst counter. In the burst mode, the
IDT71V547 can provide four cycles of data for a single address presented
to the SRAM. The order of the burst sequence is defined by the
LBO
input
pin. The
LBO
pin selects between linear and interleaved burst sequence.
The ADV/LD signal is used to load a new external address (ADV/LD =
LOW) or increment the internal burst counter (ADV/LD = HIGH).
The IDT71V547 SRAM utilizes IDT's high-performance, high-volume
3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x
20mm 100-pin thin plastic quad flatpack (TQFP) for high board density.
Pin Description Summary
A
0
- A
16
CE
1
, CE
2
,
CE
2
OE
R/W
CEN
BW
1
,
BW
2
,
BW
3
,
BW
4
CLK
ADV/LD
LBO
I/O
0
- I/O
31
, I/O
P1
- I/O
P4
V
DD
V
SS
Address Inputs
Three Chip Enables
Output Enable
Read/Write Signal
Clock Enable
Individual Byte Write Selects
Clock
Advance Burst Address / Load New Address
Linear / Interleaved Burst Order
Data Input/Output
3.3V Power
Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Static
Synchronous
Static
Static
3822 tbl 01
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.
1. Pin 14 does not have to be connected directly to V
SS
as long as the input voltage is < V
IL
.
2. Pins 83 and 84 are reserved for future A
17
(8M) and A
18
(16M) respectively.
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
Rating
Supply Voltage on VDD with
Respect to GND
DC Input Voltage
(5)
DC Voltage Applied to Outputs in
High-Z State
(5)
Operating Temperature
Ambient Temperature with Power
Applied (Temperature Under
Bias)
Storage Temperature
Current into Outputs (Low)
Static Discharge Voltage
(per MIL-STD-883, Method 3015)
Latch-Up Current
Value
–0.5 to +3.6
–0.5 to V
DDQ
+0.5
–0.5 to V
DDQ
+0.5
0°C to 70°C
–55 to +125
Unit
V
V
V
°C
°C
(T
A
= +25°C, f = 1.0MHz, TQFP package)
Symbol
C
IN
C
I/O
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
5
7
Unit
pF
pF
3822 tbl 06
Capacitance
V
TERM
(3)
V
TERM
(4)
T
A
T
BIAS
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
T
STG
I
OUT
V
ESD
I
LU
–65 to +150
20
>2001
>200
°C
mA
V
mA
NOTES:
5284 tbl 05
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. V
DD
and Input terminals only.
3. I/O terminals.
4
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Flow-Through Outputs
™
Commercial and Industrial Temperature Ranges
Synchronous Truth Table
(1)
CEN
L
L
L
L
L
L
H
R/W
L
H
X
X
X
X
X
Chip
(5)
Enable
Select
Select
X
X
Deselect
X
X
ADV/LD
L
L
H
H
L
H
X
BWx
Valid
X
Valid
X
X
X
X
ADDRESS
USED
External
External
Internal
Internal
X
X
X
PREVIOUIS CYCLE
X
X
LOAD WRITE/
BURST WRITE
LOAD READ/
BURST READ
X
DESELECT / NOOP
X
CURRENT CYCLE
LOAD WRITE
LOAD READ
BURST WRITE
(Advance Burst Counter)
(2)
BURST READ
(Advance Burst Counter)
(2)
DESELECT or STOP
(3)
NOOP
SUSPEND
(4)
I/O
(1 cycle later)
D
(7)
Q
(7)
D
(7)
Q
(7)
HiZ
HiZ
Previous Value
3822 tbl 07
NOTES:
1. L = V
IL
, H = V
IH
, X = Don’t Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature
of the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (CE
1
, or
CE
2
is sampled high or CE
2
is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus
will tri-state one cycle after deselect is initiated.
4. When
CEN
is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the
I/Os remains unchanged.
5. To select the chip requires
CE
1
= L,
CE
2
= L and CE
2
= H on these chip enable pins. The chip is deselected if either one of thechip enable is false.
6. Device Outputs are ensured to be in High-Z during device power-up.
7. Q - data read from the device, D - data written to the device.
Partial Truth Table for Writes
(1)
Operation
READ
WRITE ALL BYTES
WRITE BYTE 1 (I/O [0:7], I/O
P1
)
(2)
WRITE BYTE 2 (I/O [8:15], I/O
P2
)
(2)
WRITE BYTE 3 (I/O [16:23], I/O
P3
)
(2)
WRITE BYTE 4 (I/O [24:31], I/O
P4
)
(2)
NO WRITE
NOTES:
1. L = V
IL
, H = V
IH
, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
