3.3 V
OLT
Time S
LOT
I
NTERCHANGE
D
IGITAL
S
WITCH
1,024 x 1,024
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
IDT72V70810
DATASHEET
1,024 x 1,024 channel non-blocking switching at 8.192 Mb/s
Per-channel variable or constant throughput delay
Automatic identification of ST-BUS
®
/GCI interfaces
Accepts 8 Serial Data Streams of 8.192 Mb/s
Automatic frame offset delay measurement
Per-stream frame delay offset programming
Per-channel high impedance output control
Per-channel Processor Mode
Control interface compatible to Intel/Motorola CPUs
Connection memory block programming
Available in 64-pin Thin Plastic Quad Flatpack (TQFP) and
64-pin Small Thin Quad Flatpack (STQFP)
3.3V Power Supply
Operating Temperature Range -40°C to +85°C
3.3V I/O with 5V Tolerant Inputs
DESCRIPTION:
The IDT72V70810 is a non-blocking digital switch that has a capacity
of 1,024 x 1,024 channels at a serial bit rate of 8.192 Mb/s. Some of the
main features are: programmable stream and channel control, Processor
Mode, input offset delay and high-impedance output control.
Per-stream input delay control is provided for managing large multi-chip
switches that transport both voice channel and concatenated data channels.
In addition, input streams can be individually calibrated for input frame offset.
FUNCTIONAL BLOCK DIAGRAM
IDT72V70810 REVISION A JUNE 9, 2014
1
©2014 Integrated Device Technology, Inc.
IDT 72V70810 Data Sheet
3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH 1,024 x 1,024
PIN CONFIGURATION
TQFP 0.80mm pitch, 14mm x 14mm (PN64-1, order code: PF)
STQFP 0.50 pitch, 10mm x 10mm (PP64-1, order code: TF)
TOP VIEW
NOTES:
1. DNC - Do Not Connect.
2. All I/O pins are 5V tolerant.
IDT72V70810 REVISION A JUNE 9, 2014
2
©2014 Integrated Device Technology, Inc.
IDT 72V70810 Data Sheet
3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH 1,024 x 1,024
PIN DESCRIPTION
Symbol
GND
Vcc
TX0-7
RX0-7
F0i
Ground.
Vcc
TX Output 0 to 7
(Three-state Outputs)
RX Input 0 to 7
Frame Pulse
O
I
I
NAME
I/O
Ground Rail.
+3.3 Volt Power Supply.
Serial data output stream. These streams have a data rate of 8.192 Mb/s.
Serial data input stream. These streams have a data rate of 8.192 Mb/s.
When the WFPS pin is LOW, this input accepts and automatically identifies frame synchronization signals formatted
according to ST-BUS® and GCI specifications. When the WFPS pin is HIGH, this pin accepts a negative frame pulse
which conforms to WFPS formats.
When the WFPS pin is LOW, this pin is the frame measurement input. When the WFPS pin is HIGH, the HCLK (4.096
MHz clock) is required for frame alignment in the wide frame pulse (WFP) mode.
Serial clock for shifting data in/out on the serial streams (RX/TX 0-7). This input accepts a 16.384 MHz clock.
This input (active LOW) puts the IDT72V70810 in its reset state that clears the device internal counters, registers and
brings TX0-7 and microport data outputs to a high-impedance state. The time constant for a power up reset circuit
must be a minimum of five times the rise time of the power supply. In normal operation, the
RESET
pin must be held
LOW for a minimum of 100ns to reset the device.
When 1, enables the wide frame pulse (WFP) Frame Alignment interface. When 0, the device operates in ST-BUS®/
GCI mode.
When non-multiplexed CPU bus operation is selected, these lines provide the A0-A7 address lines to the internal
memories.
For Motorola multiplexed bus operation, this input is DS. This active HIGH DS input works in conjunction with
CS
to
enable the read and write operations. For Motorola non-multiplexed CPU bus operation, this input is DS. This active
LOW input works in conjunction with
CS
to enable the read and write operations. For Intel multiplexed bus operation,
this input is
RD.
This active LOW input sets the data bus lines (AD0-7, D8-15) as outputs.
In the cases of Motorola non-multiplexed and multiplexed bus operations, this input is R/W. This input controls the
direction of the data bus lines (AD0-7, D8-15) during a microprocessor access. For Intel multiplexed bus operation,
this input is
WR.
This active LOW input is used with
RD
to control the data bus (AD0-7) lines as inputs.
Active LOW input used by a microprocessor to activate the microprocessor port of IDT72V70810.
This input is used if multiplexed bus operation is selected via the IM input pin. For Motorola non-multiplexed bus opera-
tion, connect this pin to ground.
When IM is HIGH, the microprocessor port is in the multiplexed mode. When IM is LOW, the microprocessor port is in
non-multiplexed mode.
These pins are the eight least significant data bits of the microprocessor port. In multiplexed mode, these pins are also
the input address bits of the microprocessor port.
These pins are the eight most significant data bits of the microprocessor port.
This active LOW output signal indicates that a data bus transfer is complete. When the bus cycle ends, this pin drives
HIGH and then goes high-impedance, allowing for faster bus cycles with a weaker pull-up resistor. A pull-up resistor is
required to hold a HIGH level when the pin is in high-impedance.
This is a 16.384 Mb/s output containing 2.048 bits per frame respectively. The level of each bit is determinedby the
CCO bit in the connection memory. See External Drive Control Section.
This is the output enable control for the TX0 to TX7 serial outputs. When ODE input is LOW and the OSB bit of the
IMS register is LOW, TX0-7 are in a high-impedance state. If this input is HIGH, the TX0-7 output drivers are enabled.
However, each channel may still be put into a high-impedance state by using the per channel control bit in the connec-
tion memory.
Description
FE/HCLK
CLK
RESET
Frame Evaluation/
HCLK Clock
Clock
Device Reset
(Schmitt Trigger Input)
I
I
I
WFPS
A0-7
DS/RD
Wide Frame
Pulse Select
Address 0-7
Data Strobe/Read
I
I
I
R/W /
WR
Read/Write / Write/Read
I
CS
AS/ALE
IM
AD0-7
D8-15
DTA
Chip Select
Address Strobe or
Latch Enable
CPU Interface Mode
Address/Data Bus 0 to 7
Data Bus 8-15
Data Transfer
Acknowledgment
Control Output
Output Drive Enable
I
I
I
I/O
I/O
O
CCO
ODE
O
I
IDT72V70810 REVISION A JUNE 9, 2014
3
©2014 Integrated Device Technology, Inc.
IDT 72V70810 Data Sheet
3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH 1,024 x 1,024
The IDT72V70810 is capable of switching up to 1,024 x 1,024, 64 Kbit/s
PCM or N x 64 Kbit/s channel data. The device maintains frame integrity in
data applications and minimum throughput delay for voice applications on a
per channel basis.
The serial input streams of the IDT72V70810 have a bit rate of 8.192 Mb/s
and are arranged in 125ms wide frames, which contain 128 channels. The
data rates on input and output streams are identical.
In Processor Mode, the microprocessor can access input and output
time-slots on a per channel basis allowing for transfer of control and status
information. The IDT72V70810 automatically identifies the polarity of the
frame synchronization input signal and configures the serial streams to either
ST-BUS
®
or GCI formats.
With the variety of different microprocessor interfaces, IDT72V70810 has
provided an Input Mode pin (IM) to help integrate the device into different
microprocessor based environments: Non-multiplexed or Multiplexed. These
interfaces provide compatibility with multiplexed and Motorola non-multiplexed
buses. The device can also resolve different control signals eliminating the
use of glue logic necessary to convert the signals (R/W/WR, DS/RD, AS/ALE).
The frame offset calibration function allows users to measure the frame
offset delay using a frame evaluation pin (FE). The input offset delay can be
programmed for individual streams using internal frame input offset registers,
see Table 8.
The internal loopback allows the TX output data to be looped around to
the RX inputs for diagnostic purposes.
A functional Block Diagram of the IDT72V70810 is shown in Figure 1.
DATA AND CONNECTION MEMORY
The received serial data is converted to parallel format by internal seri-
al-to-parallel converters and stored sequentially in the data memory. The 8 KHz
input frame pulse (F0i) is used to generate channel and frame boundaries of
the input serial data. Depending on the interface mode select (IMS) register,
the usable data memory may be as large as 1,024 bytes.
Data to be output on the serial streams (TX0-7) may come from either
the data memory or connection memory. For data output from data memory
(connection mode), addresses in the connection memory are used. For data to
be output from connection memory, the connection memory control bits must
set the particular TX output in Processor Mode. One time-slot before the data
is to be output, data from either connection memory or data memory is read
internally. This allows enough time for memory access and parallel-to-serial
conversion.
Clock is required for data and connection memory access.
CONNECTION AND PROCESSOR MODES
In the Connection Mode, the addresses of the input source data for all
output channels are stored in the connection memory. The connection mem-
ory is mapped in such a way that each location corresponds to an output
channel on the output streams. For details on the use of the source address
data (CAB and SAB bits), see Table 10. Once the source address bits are
programmed by the microprocessor, the contents of the data memory at the
selected address are transferred to the parallel-to-serial converters and then
onto a TX output stream.
By having the each location in the connection memory specify an input
channel, multiple outputs can specify the same input address. This can be
a powerful tool used for broadcasting data.
IDT72V70810 REVISION A JUNE 9, 2014
4
FUNCTIONAL DESCRIPTION
In Processor Mode, the microprocessor writes data to the connection
memory. Each location in the connection memory corresponds to a par-
ticular output stream and channel number and is transferred directly to the
parallel-to-serial converter one time-slot before it is to be output. This data
will be output on the TX streams in every frame until the data is changed by
the microprocessor.
As the IDT72V70810 can be used in a wide variety of applications, the
device also has memory locations to control the outputs based on operating
mode. Specifically, the IDT72V70810 provides five per-channel control
bits for the following functions: processor or connection mode, constant or
variable delay, enables/three-state the TX output drivers and enables/disable
the loopback function. In addition, one of these bits allows the user to control
the CCO output.
If an output channel is set to a high-impedance state through the connection
memory, the TX output will be in a high-impedance state for the duration of that
channel. In addition to the per-channel control, all channels on the ST-BUS
®
outputs can be placed in a high impedance state by either pulling the ODE
input pin low or programming the Output Stand-By (OSB) bit in the interface
mode selection register. This action overrides the per-channel programming
in the connection memory bits.
The connection memory data can be accessed via the microprocessor
interface. The addressing of the devices internal registers, data and connection
memories is performed through the address input pins and the Memory Select
(MS) bit of the control register. For details on device addressing, see Software
Control and Control Register bits description (Table 3 and 5).
SERIAL DATA INTERFACE TIMING
The master clock frequency must always be twice the data rate. For serial
data rates of 8.192 Mb/s, the master clock (CLK) must be 16.384 MHz. The
input and output stream data rates will always be identical.
The IDT72V70810 provides two different interface timing modes ST-BUS
®
/
GCI and WFP (wide frame pulse). If the WFPS pin is high, the IDT72V70810
is in the wide frame pulse (WFP) frame alignment mode.
In ST-BUS
®
/GCI mode, the input 8 KHz frame pulse can be in either
ST-BUS
®
or GCI format. The IDT72V70810 automatically detects the pres-
ence of an input frame pulse and identifies it as either ST-BUS
®
or GCI. In
ST-BUS
®
format, every second falling edge of the master clock marks a bit
boundary and the data is clocked in on the rising edge of CLK, three quarters
of the way into the bit cell, see Figure 7. In GCI format, every second rising
edge of the master clock marks the bit boundary and data is clocked in on the
falling edge of CLK at three quarters of the way into the bit cell, see Figure 8.
WIDE FRAME PULSE (WFP) FRAME ALIGNMENT TIMING
When the device is in WFP frame alignment mode, the CLK input must be
at 16.384 MHz, the FE/HCLK input is 4.096 MHz and the 8 KHz frame pulse
is in ST-BUS
®
format. The timing relationship between CLK, HCLK and the
frame pulse is shown in Figure 9.
When WFPS pin is high, the frame alignment evaluation feature is dis-
abled. However, the frame input offset registers may still be programmed to
compensate for the varying frame delays on the serial input streams.
INPUT FRAME OFFSET SELECTION
Input frame offset selection allows the channel alignment of individual
input streams to be offset with respect to the output stream channel alignment
(i.e.
F0i).
Although all input data comes in at the same speed, delays can be
©2014 Integrated Device Technology, Inc.
IDT 72V70810 Data Sheet
3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH 1,024 x 1,024
caused by variable path serial backplanes and variable path lengths which
may be implemented in large centralized and distributed switching systems.
Because data is often delayed, this feature is useful in compensating for the
skew between clocks.
Each input stream can have its own delay offset value by programming
the frame input offset registers (FOR). The maximum allowable skew is +4.5
master clock (CLK) periods forward with resolution of ½ clock period. The
output frame offset cannot be offset or adjusted. See Figure 5, Table 8 and
9 for delay offset programming.
SERIAL INPUT FRAME ALIGNMENT EVALUATION
The IDT72V70810 provides the frame evaluation (FE) input to determine
different data input delays with respect to the frame pulse
F0i.
A measurement cycle is started by setting the start frame evaluation (SFE)
bit low for at least one frame. When the SFE bit in the IMS register is changed
from low to high, the evaluation starts. Two frames later, the complete frame
evaluation (CFE) bit of the frame alignment register (FAR) changes from low
to high to signal that a valid offset measurement is ready to be read from bits
0 to 11 of the FAR register. The SFE bit must be set to zero before a new
measurement cycle started.
In ST-BUS
®
mode, the falling edge of the frame measurement signal (FE) is
evaluated against the falling edge of the ST-BUS
®
frame pulse. In GCI mode,
the rising edge of FE is evaluated against the rising edge of the GCI frame
pulse. See Table 7 & Figure 4 for the description of the frame alignment register.
This feature is not available when the WFP Frame Alignment mode is
enabled (i.e., when the WFPS pin is connected to VCC).
MEMORY BLOCK PROGRAMMING
The IDT72V70810 provides users with the capability of initializing the
entire connection memory block in two frames. To set bits 11 to 15 of every
connection memory location, first program the desired pattern in bits 5 to 9
of the IMS register.
The block programming mode is enabled by setting the memory block
program (MBP) bit of the control register high. When the block programming
enable (BPE) bit of the IMS register is set to high, the block programming data
will be loaded into the bits 11 to 15 of every connection memory location. The
other connection memory bits (bit 0 to bit 10) are loaded with zeros. When the
memory block programming is complete, the device resets the BPE bit to zero.
LOOPBACK CONTROL
The loopback control (LPBK) bit of each connection memory location
allows the TX output data to be looped backed internally to the RX input for
diagnostic purposes.
If the LPBK bit is high, the associated TX output channel data is internally
looped back to the RX input channel (i.e., data from TX n channel m routes to
the RX n channel m internally); if the LPBK bit is low, the loopback feature is
disabled. For proper per-channel loopback operation, the contents of frame
delay offset registers must be set to zero.
delay is best as it ensures minimum delay between input and output data. In
wideband data applications, constant throughput delay is best as the frame
integrity of the information is maintained through the switch.
The delay through the device varies according to the type of throughput
delay selected in the
V/C
bit of the connection memory.
VARIABLE DELAY MODE (V/C BIT = 0)
In this mode, the delay is dependent only on the combination of source
and destination channels and is independent of input and output streams.
The minimum delay achievable in the IDT72V70810 is three time-slots. If
the input channel data is switched to the same output channel (channel n,
frame p), it will be output in the following frame (channel n, frame p+1). The
same is true if input channel n is switched to output channel n+1 or n+2. If
the input channel n is switched to output channel n+3, n+4,..., the new output
data will appear in the same frame. Table 1 shows the possible delays for the
IDT72V70810 in the variable delay mode.
CONSTANT DELAY MODE (V/C BIT = 1)
In this mode, frame integrity is maintained in all switching configurations
by making use of a multiple data memory buffer. Input channel data is written
into the data memory buffers during frame n will be read out during frame
n+2. In the IDT72V70810, the minimum throughput delay achievable in the
constant delay mode will be one frame. See Table 2 for possible delays in
constant delay mode.
MICROPROCESSOR INTERFACE
The IDT72V70810 provides a parallel microprocessor interface for mul-
tiplexed or non-multiplexed bus structures. This interface is compatible with
Motorola non-multiplexed and multiplexed buses.
If the IM pin is low a Motorola non-multiplexed bus should be connected
to the device. If the IM pin is high, the device monitors the AS/ALE and DS/
RD
to determine what mode the IDT72V70810 should operate in.
If DS/RD is low at the rising edge of AS/ALE, then the mode 1 multiplexed
timing is selected. If DS/RD is high at the rising edge of AS/ALE, then the
mode 2 multiplexed bus timing is selected.
For multiplexed operation, the required signals are the 8-bit data and ad-
dress (AD0-AD7), 8-bit Data (D8-D15), Address strobe/Address latch enable
(AS/ ALE), Data strobe/Read (DS/RD), Read/Write /Write (R/W /
WR),
Chip
select (CS) and Data transfer acknowledge (DTA). See Figure 12 and Figure
13 for multiplexed parallel microport timing.
For the Motorola non-multiplexed bus, the required signals are the 16-bit
data bus (AD0-AD7, D8-D15), 8-bit address bus (A0-A7) and 4 control lines
(CS, DS, R/W and
DTA).
See Figure 14 and 15 for Motorola non-multiplexed
microport timing.
The IDT72V70810 microport provides access to the internal registers,
connection and data memories. All locations provide read/write access except
for the data memory and the frame alignment register which are read only.
MEMORY MAPPING
The address bus on the microprocessor interface selects the internal
registers and memories of the IDT72V70810.
If the A7 address input is low, then A6 through A0 are used to address the
interface mode selection (IMS), control (CR), frame alignment (FAR) and frame
input offset (FOR) registers (Table 4). If the A7 is high, then A6 through A0 are
5
©2014 Integrated Device Technology, Inc.
DELAY THROUGH THE IDT72V70810
The switching of information from the input serial streams to the output
serial streams results in a throughput delay. The device can be programmed
to perform time-slot interchange functions with different throughput delay ca-
pabilities on the per-channel basis. For voice applications, variable throughput
IDT72V70810 REVISION A JUNE 9, 2014
嵌入式系统
