3.3 VOLT HIGH-DENSITY SUPERSYNC II™ 72-BIT FIFO
512 x 72, 1,024 x 72
2,048 x 72, 4,096 x 72
8,192 x 72, 16,384 x 72
32,768 x 72, 65,536 x 72
IDT72V7230, IDT72V7240
IDT72V7250, IDT72V7260
IDT72V7270, IDT72V7280
IDT72V7290, IDT72V72100
FEATURES:
•
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Choose among the following memory organizations:
IDT72V7230
⎯
512 x 72
IDT72V7240
⎯
1,024 x 72
IDT72V7250
⎯
2,048 x 72
IDT72V7260
⎯
4,096 x 72
IDT72V7270
⎯
8,192 x 72
IDT72V7280
⎯
16,384 x 72
IDT72V7290
⎯
32,768 x 72
IDT72V72100
⎯
65,536 x 72
100 MHz operation (10 ns read/write cycle time)
User selectable input and output port bus-sizing
- x72 in to x72 out
- x72 in to x36 out
- x72 in to x18 out
- x36 in to x72 out
- x18 in to x72 out
Big-Endian/Little-Endian user selectable word representation
Fixed, low first word latency
Zero latency retransmit
Auto power down minimizes standby power consumption
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Empty, Full and Half-Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
Program programmable flags by either serial or parallel means
Select IDT Standard timing (using
EF
and
FF
flags) or First Word
Fall Through timing (using
OR
and
IR
flags)
Output enable puts data outputs into high impedance state
Easily expandable in depth and width
Independent Read and Write Clocks (permit reading and writing
simultaneously)
Asynchronous operation of Output Enable,
OE
Read Chip Select (
RCS
) on Read Side
Available in a 256-pin Fine Pitch Ball Grid Array package (PBGA)
Features JTAG (Boundary Scan)
High-performance submicron CMOS technology
Industrial temperature range (–40°C to +85°C) is available
°
°
FUNCTIONAL BLOCK DIAGRAM
D
0
-D
n
(x72, x36 or x18)
WEN
WCLK
LD
SEN
SCLK
INPUT REGISTER
OFFSET REGISTER
FF/IR
PAF
EF/OR
PAE
HF
FWFT/SI
PFM
FSEL0
FSEL1
WRITE CONTROL
LOGIC
WRITE POINTER
RAM ARRAY
512 x 72
1,024 x 72
2,048 x 72
4,096 x 72
8,192 x 72
16,384 x 72
32,768 x 72
65,536 x 72
FLAG
LOGIC
READ POINTER
BE
IP
BM
IW
OW
MRS
PRS
TCK
TRST
TMS
TDO
TDI
CONTROL
LOGIC
BUS
CONFIGURATION
RESET
LOGIC
JTAG
CONTROL
(BOUNDARY SCAN)
OUTPUT REGISTER
READ
CONTROL
LOGIC
RT
RM
RCLK
REN
RCS
Q
0
-Q
n
(x72, x36 or x18)
4680 drw01
OE
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SuperSync II FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
JANUARY 2009
DSC-4680/11
1
©
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II
TM
FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
COMMERCIAL TEMPERATURE RANGE
DESCRIPTION:
The IDT72V7230/72V7240/72V7250/72V7260/72V7270/72V7280/
72V7290/72V72100 are exceptionally deep, high speed, CMOS First-In-First-
Out (FIFO) memories with clocked read and write controls and a flexible Bus-
Matching x72/x36/x18 data flow. These FIFOs offer several key user benefits:
• Flexible x72/x36/x18 Bus-Matching on both read and write ports
• The period required by the retransmit operation is fixed and short.
• The first word data latency period, from the time the first word is written to an
empty FIFO to the time it can be read, is fixed and short.
• High density offerings up to 4 Mbit
Bus-Matching Sync FIFOs are particularly appropriate for network, video,
telecommunications, data communications and other applications that need to
buffer large amounts of data and match busses of unequal sizes.
Each FIFO has a data input port (D
n
) and a data output port (Q
n
), both of
which can assume either a 72-bit, 36-bit or a 18-bit width as determined by the
state of external control pins Input Width (IW), Output Width (OW), and Bus-
Matching (BM) pin during the Master Reset cycle.
The input port is controlled by a Write Clock (WCLK) input and a Write Enable
(WEN) input. Data is written into the FIFO on every rising edge of WCLK when
WEN
is asserted. The output port is controlled by a Read Clock (RCLK) input
PIN CONFIGURATION
A1 BALL PAD CORNER
A
Q33
Q35
Q34
Q30
Q28
Q16
Q13
Q10
Q61
Q58
Q55
Q43
Q40
Q37
Q25
Q21
Q22
Q47
Q46
Q45
Q27
Q15
Q12
Q9
Q60
Q57
Q54
Q42
Q39
Q36
Q18
Q19
Q20
Q50
Q49
Q48
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
RT
Q6
Q7
Q8
Q53
Q52
Q51
GND
GND
GND
Q65
Q64
Q63
Q68
Q67
Q66
Q71
Q70
Q69
TCK
VCC
VCC
VCC
VCC
VCC
VCC
D71
D70
D69
TDI
GND
D68
D67
D66
D65
D64
D63
D53
D52
D51
TMS
VCC
VCC
VCC
VCC
VCC
VCC
GND
D50
D49
D48
GND
GND
GND
GND
GND
GND
GND
IW
D47
D46
D45
D27
D15
D12
D9
D60
D57
D54
D42
D35
D34
D30
D28
D16
D13
D10
D61
D58
D55
D43
D40
D37
D25
D21
D22
D33
D32
D31
D29
D17
D14
D11
D62
D59
D56
D44
D41
D38
D26
D24
D23
B
Q32
C
Q31
D
Q29
VCC GND
VCC
VCC
GND
GND
GND
GND
GND
GND
TRST
TDO
VCC
GND
GND
GND
GND
GND
GND
GND
OW
E
Q17
F
Q14
GND VCC
GND
GND
GND
VCC
VCC
VCC
G
Q11
GND VCC
GND VCC
GND VCC
GND
GND
GND
RM
Q3
Q4
Q5
VCC
VCC
VCC
PFM
Q0
Q1
Q2
H
Q62
J
Q59
K
Q56
GND VCC
GND
FS1
BE
MRS
PAF
FF
VCC
FS0
HF
PRS
WEN
WCLK
L
Q44
GND VCC
GND
BM
RCS
OE
GND
IP
PAE
EF
M
Q41
GND SCLK D39
SEN
D6
D7
D8
D36
D18
D19
D20
N
Q38
FWFT/
LD
SI
D0
D1
D2
D3
D4
D5
P
Q26
R
Q24
T
Q23
REN
RCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
4680 drw02
PBGA (BB256-1, order code: BB)
TOP VIEW
2
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II
TM
FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
COMMERCIAL TEMPERATURE RANGE
DESCRIPTION (CONTINUED)
and Read Enable (REN) input. Data is read from the FIFO on every rising edge
of RCLK when
REN
is asserted. An Output Enable (OE) input is provided for
three-state control of the outputs.
A Read Chip Select (RCS) input is also provided for synchronous enable
and disable of the read port control input,
REN.
The
RCS
input is synchronized
to the read clock, and also provides three-state control of the Q
n
outputs. When
RCS
is disable,
REN
will be disabled internally and data outputs will be in
High-Impedance state.
The frequencies of both the RCLK and the WCLK signals may vary from 0
to f
MAX
with complete independence. There are no restrictions on the frequency
of the one clock input with respect to the other.
There are two possible timing modes of operation with these devices: IDT
Standard mode and First Word Fall Through (FWFT) mode.
In
IDT Standard mode,
the first word written to an empty FIFO will not appear
on the data output lines unless a specific read operation is performed. A read
operation, which consists of activating
REN
and enabling a rising RCLK edge,
will shift the word from internal memory to the data output lines.
In
FWFT mode,
the first word written to an empty FIFO is clocked directly
to the data output lines after three transitions of the RCLK signal. A
REN
does
not have to be asserted for accessing the first word. However, subsequent
words written to the FIFO do require a LOW on
REN
for access. The state of
the FWFT/SI input during Master Reset determines the timing mode in use.
For applications requiring more data storage capacity than a single FIFO
can provide, the FWFT timing mode permits depth expansion by chaining FIFOs
in series (i.e. the data outputs of one FIFO are connected to the corresponding
data inputs of the next). No external logic is required.
These FIFOs have five flag pins,
EF/OR
(Empty Flag or Output Ready),
FF/IR
(Full Flag or Input Ready),
HF
(Half-full Flag),
PAE
(Programmable
Almost-Empty flag) and
PAF
(Programmable Almost-Full flag). The
EF
and
FF
functions are selected in IDT Standard mode. The
IR
and
OR
functions are
selected in FWFT mode.
HF, PAE
and
PAF
are always available for use,
irrespective of timing mode.
PAE
and
PAF
can be programmed independently to switch at any point in
memory. Programmable offsets determine the flag switching threshold and can
be loaded by two methods: parallel or serial. Eight default offset settings are also
provided, so that
PAE
can be set to switch at a predefined number of locations
from the empty boundary and the
PAF
threshold can also be set at similar
predefined values from the full boundary. The default offset values are set during
Master Reset by the state of the FSEL0, FSEL1, and
LD
pins.
For serial programming,
SEN
together with
LD
on each rising edge of
SCLK, are used to load the offset registers via the Serial Input (SI). For parallel
programming,
WEN
together with
LD
on each rising edge of WCLK, are used
to load the offset registers via D
n
.
REN
together with
LD
on each rising edge
of RCLK can be used to read the offsets in parallel from Q
n
regardless of whether
serial or parallel offset loading has been selected.
PARTIAL RESET (PRS)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
(x72, x36, x18) DATA IN (D
0
- D
n
)
SERIAL IN CLOCK(SCLK)
SERIAL ENABLE(SEN)
FIRST WORD FALL THROUGH/SERIAL INPUT
(FWFT/SI)
FULL FLAG/INPUT READY (FF/IR)
PROGRAMMABLE ALMOST-FULL (PAF)
INTERSPERSED/
NON-INTERSPERSED PARITY (IP)
BIG-ENDIAN/LITTLE-ENDIAN (BE)
MASTER RESET (MRS)
READ CLOCK (RCLK)
READ ENABLE (REN)
READ CHIP SELECT (RCS)
OUTPUT ENABLE (OE)
(x72, x36, x18) DATA OUT (Q
0
- Q
n
)
RETRANSMIT (RT)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
HALF-FULL FLAG (HF)
JTAG CLOCK (TCLK)
JTAG RESET (TRST)
JTAG MODE (TMS)
(TDO)
(TDI)
IDT
72V7230
72V7240
72V7250
72V7260
72V7270
72V7280
72V7290
72V72100
INPUT WIDTH (IW)
OUTPUT WIDTH (OW)
BUS-
MATCHING
(BM)
4680 drw03
Figure 1. Single Device Configuration Signal Flow Diagram
3
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II
TM
FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
COMMERCIAL TEMPERATURE RANGE
During Master Reset (MRS) the following events occur: the read and write
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
Standard mode or FWFT mode.
The Partial Reset (PRS) also sets the read and write pointers to the first
location of the memory. However, the timing mode, programmable flag
programming method, and default or programmed offset settings existing before
Partial Reset remain unchanged. The flags are updated according to the timing
mode and offsets in effect.
PRS
is useful for resetting a device in mid-operation,
when reprogramming programmable flags would be undesirable.
It is also possible to select the timing mode of the
PAE
(Programmable Almost-
Empty flag) and
PAF
(Programmable Almost-Full flag) outputs. The timing
modes can be set to be either asynchronous or synchronous for the
PAE
and
PAF
flags.
If asynchronous
PAE/PAF
configuration is selected, the
PAE
is asserted
LOW on the LOW-to-HIGH transition of RCLK.
PAE
is reset to HIGH on the LOW-
to-HIGH transition of WCLK. Similarly, the
PAF
is asserted LOW on the LOW-
to-HIGH transition of WCLK and
PAF
is reset to HIGH on the LOW-to-HIGH
transition of RCLK.
If synchronous
PAE/PAF
configuration is selected , the
PAE
is asserted and
updated on the rising edge of RCLK only and not WCLK. Similarly,
PAF
is
asserted and updated on the rising edge of WCLK only and not RCLK. The
mode desired is configured during master reset by the state of the Programmable
Flag Mode (PFM) pin.
The Retransmit function allows data to be reread from the FIFO more than
once. A LOW on the
RT
input during a rising RCLK edge initiates a retransmit
operation by setting the read pointer to the first location of the memory array.
A zero-latency retransmit timing mode can be selected using the Retransmit
timing Mode pin (RM). During Master Reset, a LOW on RM will select zero
latency retransmit. A HIGH on RM during Master Reset will select normal
latency.
If zero latency retransmit operation is selected, the first data word to be
retransmitted will be placed on the output register with respect to the same RCLK
edge that initiated the retransmit based on RT being LOW.
Refer to Figure 16 and 17 for
Retransmit Timing
with normal latency. Refer
to Figure 18 and 19 for
Zero Latency Retransmit Timing.
The device can be configured with different input and output bus widths as
shown in Table 1.
A Big-Endian/Little-Endian data word format is provided. This function is
useful when the FIFO is used in Bus-Matching mode, to determine order of the
words. As an example, if Big-Endian mode is selected, then the most significant
word of the long word written into the FIFO will be read out of the FIFO first,
followed by the least significant word. If Little-Endian format is selected, then the
least significant word of the long word written into the FIFO will be read out first,
followed by the most significant word. The mode desired is configured during
master reset by the state of the Big-Endian (BE) pin.
The Interspersed/Non-Interspersed Parity (IP) bit function allows the user
to select the parity bit in the word loaded into the parallel port (D0-Dn) when
programming the flag offsets. If Interspersed Parity mode is selected, then the
FIFO will assume that the parity bit is located in bit position D8 during the parallel
programming of the flag offsets. If Non-Interspersed Parity mode is selected,
then D8 is assumed to be a valid bit and D16 and D17 are ignored. IP mode
is selected during Master Reset by the state of the IP input pin.
If, at any time, the FIFO is not actively performing an operation, the chip will
automatically power down. Once in the power down state, the standby supply
current consumption is minimized. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down state.
Both an Asynchronous Output Enable pin (OE) and Synchronous Read
Chip Select pin (RCS) are provided on the FIFO. The Synchronous Read
Chip Select is synchronized to the RCLK. Both the output enable and read chip
select control the output buffer of the FIFO, causing the buffer to be either HIGH
impedance or LOW impedance.
JTAG test pins are also provided, the FIFO has fully functional Boundary
Scan feature, compliant with IEEE 1149.1 Standard Test Access Port and
Boundary Scan Architecture.
The IDT72V7230/72V7240/72V7250/72V7260/72V7270/72V7280/
72V7290/72V72100 are fabricated using IDT’s high speed submicron CMOS
technology.
TABLE 1 — BUS-MATCHING CONFIGURATION MODES
BM
L
H
H
H
H
IW
X
H
H
L
L
OW
X
L
H
L
H
4
Write Port Width
x72
x36
x18
x72
x72
Read Port Width
x72
x72
x72
x36
x18
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II
TM
FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Symbol
D
0
–D
71
MRS
Name
Data Inputs
Master Reset
I/O
I
I
Description
Data inputs for a 72-, 36- or 18-bit bus. When in 36- or 18-bit mode, the unused input pins should be tied
LOW.
MRS
initializes the read and write pointers to zero and sets the output register to all zeroes. During Master Reset,
the FIFO is configured for either FWFT or IDT Standard mode, Bus-Matching configurations, one of eight
programmable flag default settings, serial or parallel programming of the offset settings, Big-Endian/Little-Endian
format, zero latency timing mode, interspersed parity, and synchronous versus asynchronous programmable
flag timing modes.
PRS
initializes the read and write pointers to zero and sets the output register to all zeroes. During Partial Reset,
the existing mode (IDT or FWFT), programming method (serial or parallel), and programmable flag settings
are all retained.
RT
asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the
EF
flag to LOW (OR to
HIGH in FWFT mode) and does not disturb the write pointer, programming method, existing timing mode or
programmable flag settings.
RT
is useful to reread data from the first physical location of the FIFO.
During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset, this pin functions
as a serial input for loading offset registers.
This pin, along with IW and BM, selects the bus width of the read port. See Table 1 for bus size configuration.
This pin, along with OW and BM, selects the bus width of the write port. See Table 1 for bus size configuration.
BM works with IW and OW to select the bus sizes for both write and read ports. See Table 1 for bus size
configuration.
During Master Reset, a LOW on
BE
will select Big-Endian operation. A HIGH on BE during Master Reset
will select Little-Endian format.
During Master Reset, a LOW on RM will select zero latency Retransmit timing Mode. A HIGH on RM will select
normal latency mode.
During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on
PFM will select Synchronous Programmable flag timing mode.
During Master Reset, a LOW on IP will select Non-Interspersed Parity mode. A HIGH will select Interspersed
Parity mode.
During Master Reset, this input along with FSEL1 and the
LD
pin, will select the default offset values for the
programmable flags
PAE
and
PAF.
There are up to eight possible settings available.
During Master Reset, this input along with FSEL0 and the
LD
pin will select the default offset values for the
programmable flags
PAE
and
PAF.
There are up to eight possible settings available.
When enabled by
WEN,
the rising edge of WCLK writes data into the FIFO and offsets into the programmable
registers for parallel programming.
WEN
enables WCLK for writing data into the FIFO memory and offset registers.
When enabled by
REN,
the rising edge of RCLK reads data from the FIFO memory and offsets from the
programmable registers. (RCS must be active).
REN
enables RCLK for reading data from the FIFO memory and offset registers. (RCS must be active).
OE
provides asynchronous control of the output impedance of Q
n.
During a Master or Partial Reset the
OE
input is the only input that provide High-Impedance control of the data outputs.
RCS
provides synchronous control of the read port and output impedance of Q
n,
synchronous to RCLK
.
During
a Master or Partial Reset the
RCS
input is don’t care, if
OE
is LOW the data outputs will be Low-Impedance
regardless of
RCS.
when enabled by
SEN,
the rising edge of SCLK writes one bit of data (present on the SI input), into the
programmable register for serial programming.
SEN
enables serial loading of programmable flag offsets.
This is a dual purpose pin. During Master Reset, the state of the
LD
input along with FSEL0 and FSEL1,
determines one of eight default offset values for the
PAE
and
PAF
flags, along with the method by which these
offset registers can be programmed, parallel or serial (see Table 2). After Master Reset, this pin enables writing
to and reading from the offset registers.
In the IDT Standard mode, the
FF
function is selected.
FF
indicates whether or not the FIFO memory is full.
In the FWFT mode, the
IR
function is selected.
IR
indicates whether or not there is space available for writing
to the FIFO memory.
5
PRS
Partial Reset
I
RT
Retransmit
I
FWFT/SI
OW
IW
BM
BE
RM
PFM
IP
FSEL0
FSEL1
WCLK
WEN
RCLK
REN
OE
RCS
First Word Fall
Through/Serial In
Output Width
Input Width
Bus-Matching
Big-Endian/
Little-Endian
Retransmit Timing
Mode
Programmable
Flag Mode
Interspersed Parity
Flag Select Bit 0
Flag Select Bit 1
Write Clock
Write Enable
Read Clock
Read Enable
Output Enable
Read Chip Select
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SCLK
SEN
LD
Serial Input Clock
Serial Enable
Load
I
I
I
FF/IR
Full Flag/
Input Ready
O
