73S1209F
Self-Contained PINpad, Smart Card Reader
IC UART to ISO7816 / EMV Bridge IC
Simplifying System Integration™
DATA SHEET
December 2008
GENERAL DESCRIPTION
The Teridian Semiconductor Corporation 73S1209F is a
versatile and economical CMOS System-on-Chip device
intended for smart card reader applications. More
generally, it is suitable anywhere a UART to ISO-7816 /
EMV bridge function is needed. The circuit is built around
an 80515 high-performance core; it features primarily an
ISO-7816 / EMV interface and a generic asynchronous
serial interface. Delivered with turnkey Teridian embedded
firmware, it forms a ready-to-use smart card reader solution
that can be seamlessly incorporated into any
microprocessor-based system where a serial line is
available.
The solution is scalable, thanks to a built-in I
2
C interface
that allows to drive external electrical smart card interfaces
such as Teridian 73S8010R/C ICs. This makes the solution
immediately able to support multi-card slots or multi-SAM
architectures.
In addition, the 73S1209F features a 5x6 PINpad interface,
9 user I/Os, 2 LED outputs (programmable current),
multiple interrupt options and an analog voltage input (for
DC voltage monitoring such as battery level detection) that
make it suitable for low-cost PINpad reader devices.
The 80515 CPU core instruction set is compatible with the
industry standard 8051, while offering one clock-cycle per
instruction processing power (most instructions). With a
CPU clock running up to 24MHz, it results in up to 24MIPS
available that meets the requirements of various encryption
needs such as AES, DES / 3-DES and even RSA (for PIN
encryption for instance).
The circuit requires a single 6MHz to 12MHz crystal.
The respective 73S1209F embedded memories are 32KB
Flash program memory, 2KB user XRAM memory, and
256B IRAM memory. Dedicated FIFOs for the ISO7816
UART are independent from the user XRAM and IRAM.
Alternatively to the turnkey firmware offered by Teridian,
customers can develop their own embedded firmware
directly within their application or using Teridian 73S1209F
Evaluation Board through a JTAG-like interface.
Overall, the Teridian 73S1209F IC requires 2 distinct power
supply voltages to operate normally with full support of all
smart card voltages, 1.8V, 3V and 5V. The digital power
supply V
DD
requires a 2.7V to 3.6V voltage, and the analog
power supply V
PC
requires typically a 4.75V to 6.0V.
While the V
DD
is used to power up the CPU core and the
digital functions of the IC, the V
PC
voltage is used to supply
the proper V
CC
voltage to the smart card interface: The chip
incorporates an low drop-out linear voltage regulator that
generates the smart card power-supply V
CC
from the power
supply source V
PC
.
Embedded Flash memory is in-system programmable
and lockable by means of on-silicon fuses. This makes
the 73S1209F suitable for both development and
production phases.
Teridian Semiconductor Corporation offers with its
73S1209F a very comprehensive set of software
libraries for EMV. Refer to the
73S12xxF Software
User’s Guide
for a complete description of the
Application Programming Interface (API Libraries) and
related Software modules.
A complete array of development and programming
tools, libraries and demonstration boards enable rapid
development and certification of readers that meet
most demanding smart card standards.
APPLICATIONS
•
UART to ISO-7816 / EMV Bridges
•
PINpad smart card readers:
o
With serial connectivity
o
Ideal for low-cost POS Terminals) & Digital
Identification (Secure Login, Gov’t ID...)
•
SIM Readers in Telecom & Personal Wireless
devices
•
Payphones and vending machines
•
General purpose smart card readers
ADVANTAGES
•
Reduced BOM
•
Low-Cost
•
Dual power supply required 3.3V and 5V
typical
•
Higher performance CPU core (up to 24MIPS)
•
Built-in EMV/ISO slot, expandable to multi-
slots
•
Powerful In-Circuit Emulation and
Programming
•
A complete set of EMV4.1 / ISO-7816
libraries
•
Turnkey PC/SC and CCID firmware and host
drivers
o
Supported OS: Windows XP, Windows
TM
Mobile; Windows CE; Linux
o
Other OS: Contact Teridian Semiconductor
Rev. 1.2
© 2008 Teridian Semiconductor Corporation
1
73S1209F Data Sheet
FEATURES
80515 Core:
•
•
•
•
•
•
1 clock cycle per instruction (most instructions)
CPU clocked up to 24MHz
32kB Flash memory with security
2kB XRAM (User Data Memory)
256 byte IRAM
Hardware watchdog timer
Communication Interfaces:
DS_1209F_004
•
Full-duplex serial interface (1200bps to
115kbps UART)
•
I
2
C Master Interface (400kbps)
Man-Machine Interface and I/Os:
•
5x6 Keyboard (hardware scanning,
debouncing and scrambling)
•
(9) User I/Os
•
Up to 2 programmable current outputs (LED)
Voltage Detection:
•
•
•
•
Analog Input (detection range: 1.0V to 2.5V)
Operating Voltage:
2.7V to 3.6V Digital power supply
4.75 to 5.5V Analog, smart card power
supply
Oscillators:
•
Single low-cost 6MHz to 12MHz crystal
•
An Internal PLL provides all the necessary clocks
to each block of the system
Interrupts:
•
Standard 80C515 4-priority level structure
•
9 different sources of interrupt to the core
Power Down Modes:
•
2 standard 80C515 Power Down and IDLE
modes
•
Extensive device power down mode
Timers:
•
(2) Standard 80C52 timers T0 and T1
•
(1) 16-bit timer
Built-in ISO-7816 Card Interface:
•
Linear regulator produces VCC for the card
(1.8V, 3V or 5V)
•
Full compliance with EMV 4.1
•
Activation/Deactivation sequencers
•
Auxiliary I/O lines (C4 and C8 signals)
•
7kV ESD protection on all interface pins
Communication with Smart Cards:
•
ISO-7816 UART for protocols T=0, T=1
•
(2) 2-Byte FIFOs for transmit and receive
•
Configured to drive multiple external Teridian
73S8010x interfaces (for multi-SAM
architectures)
Operating Temperature:
•
-40°C to 85°C
Package:
•
68-pin QFN, 44-pin QFN
Software:
•
Turnkey firmware:
o
Compliant with PC/SC, CCID, ISO7816
and EMV4.1 specifications
o
Features a Power Down mode accessible
form the host
o
Supports Plug & Play over serial interface
o
Windows® XP driver available (*)
o
Windows CE / Mobile driver available (*)
o
Linux and other OS: Upon request
•
Or for custom developments:
o
A complete set of ISO-7816, EMV4.1 and
low-level libraries are available for T=0 /
T=1
o
Two-level Application Programming
Interface (ANSI C-language libraries)
(*) Contact Teridian Semiconductor for
conditions and availability
2
Rev. 1.2
DS_1209F_004
73S1209F Data Sheet
Table of Contents
1
Hardware Description ......................................................................................................................... 8
1.1
Pin Description .............................................................................................................................. 8
1.2
Hardware Overview .................................................................................................................... 11
1.3
80515 MPU Core ........................................................................................................................ 11
1.3.1
80515 Overview ............................................................................................................. 11
1.3.2
Memory Organization .................................................................................................... 11
1.4
Program Security ........................................................................................................................ 16
1.5
Special Function Registers (SFRs) ............................................................................................ 18
1.5.1
Internal Data Special Function Registers (SFRs).......................................................... 18
1.5.2
IRAM Special Function Registers (Generic 80515 SFRs) ............................................ 19
1.5.3
External Data Special Function Registers (SFRs) ........................................................ 21
1.6
Instruction Set ............................................................................................................................. 23
1.7
Peripheral Descriptions............................................................................................................... 23
1.7.1
Oscillator and Clock Generation .................................................................................... 23
1.7.2
Power Control Modes .................................................................................................... 27
1.7.3
Interrupts ........................................................................................................................ 32
1.7.4
UART ............................................................................................................................. 39
1.7.5
Timers and Counters ..................................................................................................... 44
1.7.6
WD Timer (Software Watchdog Timer) ......................................................................... 46
1.7.7
User (USR) Ports ........................................................................................................... 49
1.7.8
Analog Voltage Comparator .......................................................................................... 51
1.7.9
LED Drivers ................................................................................................................... 53
1.7.10
I
2
C Master Interface ....................................................................................................... 54
1.7.11
Keypad Interface ............................................................................................................ 61
1.7.12
Emulator Port ................................................................................................................. 67
1.7.13
Smart Card Interface Function ...................................................................................... 68
1.7.14
VDD Fault Detect Function .......................................................................................... 102
Typical Application Schematics .................................................................................................... 103
Electrical Specification................................................................................................................... 105
3.1
Absolute Maximum Ratings ...................................................................................................... 105
3.2
Recommended Operating Conditions ...................................................................................... 105
3.3
Digital IO Characteristics .......................................................................................................... 106
3.4
Oscillator Interface Requirements ............................................................................................ 106
3.5
DC Characteristics: Analog Input ............................................................................................. 106
3.6
Smart Card Interface Requirements ......................................................................................... 107
3.7
DC Characteristics .................................................................................................................... 109
3.8
Voltage / Temperature Fault Detection Circuits ....................................................................... 109
Equivalent Circuits ......................................................................................................................... 110
4.1
Package Pin Designation (68-pin QFN) ................................................................................... 117
4.2
Package Pin Designation (44-pin QFN) ................................................................................... 118
4.3
Packaging Information .............................................................................................................. 119
Ordering Information ...................................................................................................................... 121
Related Documentation .................................................................................................................. 121
Contact Information ........................................................................................................................ 121
2
3
4
5
6
7
Revision History ...................................................................................................................................... 122
Rev. 1.2
3
73S1209F Data Sheet
DS_1209F_004
Figures
Figure 1: IC Functional Block Diagram ......................................................................................................... 7
Figure 2: Memory Map ................................................................................................................................ 15
Figure 3: Clock Generation and Control Circuits ........................................................................................ 24
Figure 4: Oscillator Circuit ........................................................................................................................... 26
Figure 5: Power-Down Control .................................................................................................................... 27
Figure 6: Detail of Power-Down Interrupt Logic .......................................................................................... 28
Figure 7: Power-Down Sequencing ............................................................................................................ 28
Figure 8: External Interrupt Configuration ................................................................................................... 32
Figure 9: I
2
C Write Mode Operation ........................................................................................................... 55
Figure 10: I
2
C Read Operation .................................................................................................................... 56
Figure 11: Simplified Keypad Block Diagram.............................................................................................. 61
Figure 12: Keypad Interface Flow Chart ..................................................................................................... 63
Figure 13: Smart Card Interface Block Diagram ......................................................................................... 68
Figure 14: External Smart Card Interface Block Diagram........................................................................... 69
Figure 15: Asynchronous Activation Sequence Timing .............................................................................. 72
Figure 16: Deactivation Sequence .............................................................................................................. 72
Figure 17: Smart Card CLK and ETU Generation ...................................................................................... 73
Figure 18: Guard, Block, Wait and ATR Time Definitions ........................................................................... 74
Figure 19: Synchronous Activation ............................................................................................................. 76
Figure 20: Example of Sync Mode Operation: Generating/Reading ATR Signals ..................................... 76
Figure 21: Creation of Synchronous Clock Start/Stop Mode Start Bit in Sync Mode ................................. 77
Figure 22: Creation of Synchronous Clock Start/Stop Mode Stop Bit in Sync Mode ................................. 77
Figure 23: Operation of 9-bit Mode in Sync Mode ...................................................................................... 78
Figure 24: 73S1209F Typical PINpad, Smart Card Reader Application Schematic ................................. 103
Figure 25: 73S1209F Typical SIM / Smart Card Reader Application Schematic ..................................... 104
Figure 26: 12 MHz Oscillator Circuit ......................................................................................................... 110
Figure 27: Digital I/O Circuit ...................................................................................................................... 110
Figure 28: Digital Output Circuit ................................................................................................................ 111
Figure 29: Digital I/O with Pull Up Circuit .................................................................................................. 111
Figure 30: Digital I/O with Pull Down Circuit ............................................................................................. 112
Figure 31: Digital Input Circuit ................................................................................................................... 112
Figure 32: Keypad Row Circuit ................................................................................................................. 113
Figure 33: Keypad Column Circuit ............................................................................................................ 113
Figure 34: LED Circuit ............................................................................................................................... 114
Figure 35: Test and Security Pin Circuit ................................................................................................... 114
Figure 36: Analog Input Circuit.................................................................................................................. 115
Figure 37: Smart Card Output Circuit ....................................................................................................... 115
Figure 38: Smart Card I/O Circuit.............................................................................................................. 116
Figure 39: PRES Input Circuit ................................................................................................................... 116
Figure 40:
PRES
Input Circuit ................................................................................................................... 116
Figure 41: 73S1209F Pinout ..................................................................................................................... 117
Figure 42: 73S1209F Pinout ..................................................................................................................... 118
Figure 43: 73S1209F 68 QFN Pinout ....................................................................................................... 119
Figure 44: 73S1209F 44 QFN Pinout ....................................................................................................... 120
4
Rev. 1.2
DS_1209F_004
73S1209F Data Sheet
Tables
Table 1: 73S1209F Pinout Description ......................................................................................................... 8
Table 2: MPU Data Memory Map................................................................................................................ 11
Table 3: Flash Special Function Registers ................................................................................................. 13
Table 4: Internal Data Memory Map ........................................................................................................... 14
Table 5: Security Control Registers ............................................................................................................ 17
Table 6: IRAM Special Function Registers Locations ................................................................................. 18
Table 7: IRAM Special Function Registers Reset Values........................................................................... 19
Table 8: XRAM Special Function Registers Reset Values ......................................................................... 21
Table 9: PSW Register Flags ...................................................................................................................... 22
Table 10: Port Registers ............................................................................................................................. 23
Table 11: Frequencies and Mcount Values for MCLK = 96MHz ................................................................ 25
Table 12: The MCLKCtl Register ................................................................................................................ 25
Table 13: The MPUCKCtl Register ............................................................................................................. 26
Table 14: The INT5Ctl Register .................................................................................................................. 29
Table 15: The MISCtl0 Register .................................................................................................................. 29
Table 16: The MISCtl1 Register .................................................................................................................. 30
Table 17: The MCLKCtl Register ................................................................................................................ 30
Table 18: The PCON Register .................................................................................................................... 31
Table 19: The IEN0 Register....................................................................................................................... 33
Table 20: The IEN1 Register....................................................................................................................... 34
Table 21: The IEN2 Register....................................................................................................................... 34
Table 22: The TCON Register .................................................................................................................... 35
Table 23: The T2CON Register .................................................................................................................. 35
Table 24: The IRCON Register ................................................................................................................... 36
Table 25: External MPU Interrupts .............................................................................................................. 36
Table 26: Control Bits for External Interrupts .............................................................................................. 37
Table 27: Priority Level Groups................................................................................................................... 37
Table 28: The IP0 Register ......................................................................................................................... 37
Table 29: The IP1 Register ......................................................................................................................... 38
Table 30: Priority Levels .............................................................................................................................. 38
Table 31: Interrupt Polling Sequence .......................................................................................................... 38
Table 32: Interrupt Vectors.......................................................................................................................... 38
Table 33: UART Modes ............................................................................................................................... 39
Table 34: Baud Rate Generation ................................................................................................................ 39
Table 35: The PCON Register .................................................................................................................... 40
Table 36: The BRCON Register ................................................................................................................. 40
Table 37: The MISCtl0 Register .................................................................................................................. 41
Table 38: The S0CON Register .................................................................................................................. 42
Table 39: The S1CON Register .................................................................................................................. 43
Table 40: The TMOD Register .................................................................................................................... 44
Table 41: TMOD Register Bit Description ................................................................................................... 44
Table 42: Timers/Counters Mode Description ............................................................................................ 45
Table 43: The TCON Register .................................................................................................................... 46
Table 44: The IEN0 Register....................................................................................................................... 47
Table 45: The IEN1 Register....................................................................................................................... 47
Table 46: The IP0 Register ......................................................................................................................... 48
Table 47: The WDTREL Register ............................................................................................................... 48
Table 48: Direction Registers and Internal Resources for DIO Pin Groups ............................................... 49
Table 49: UDIR Control Bit.......................................................................................................................... 49
Table 50: Selectable Controls Using the UxIS Bits ..................................................................................... 49
Table 51: The USRIntCtl1 Register ............................................................................................................ 50
Table 52: The USRIntCtl2 Register ............................................................................................................ 50
Table 53: The USRIntCtl3 Register ............................................................................................................ 50
Table 54: The USRIntCtl4 Register ............................................................................................................ 50
Table 55: The ACOMP Register ................................................................................................................. 51
Table 56: The INT6Ctl Register .................................................................................................................. 52
Rev. 1.2
5
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