19-5404; Rev 2; 6/12
73S8024RN
Low-Cost Smart Card Interface
DATA SHEET
ADVANTAGES
•
Traditional step-up converter is replaced by a LDO
regulator:
Greatly reduced power dissipation
Fewer external components are required
Better noise performance
High current capability (90mA supplied to the card)
SO28 package is pin-to-pin compatible with
industry-standard TDA8004 and TDA8024
Card clock STOP (high and low) mode
Small format (4x4x0.85mm) 20QFN package option
True card over-current detection
Card Interface:
Complies with ISO 7816-3, EMV 4.0, and NDS
An LDO voltage regulator provides 3V / 5V to the
card from an external power supply input
Provides at least 90mA to the card
ISO 7816-3 Activation / Deactivation sequencer with
emergency automated deactivation on card removal
or fault detected by the protection circuitry
Protection includes 3 voltage supervisors that detect
voltage drops on V
CC
(card), V
DD
(digital)**, and V
PC
(regulator) power supplies
The V
DD
voltage supervisor threshold value can be
externally adjusted**
Over-current detection 150mA max
Card clock stop high or low*
2 card detection inputs, 1 for each possible user
polarity
Auxiliary I/O lines, for C4 / C8 contact signals*
Card CLK clock frequency up to 20MHz
System Controller Interface:
3 Digital inputs control the card activation /
deactivation, card reset and card voltage
4 Digital inputs control the card clock (division rate
and card clock stop modes)
1 Digital output, interrupt to the system controller,
allows the system controller to monitor the card
presence and faults.
Crystal oscillator or host clock, up to 27MHz
Regulator Power Supply:
4.75V to 5.5V (EMV 4.0)
4.85V to 5.5V (NDS)
Digital Interfacing: 2.7V to 5.5V
±6kV
ESD Protection on the card interface
Package: SO28, 20QFN or 32QFN
DESCRIPTION
The 73S8024RN is a single smart card (ICC) interface IC
that can be controlled by a dedicated control bus. The
73S8024RN has been designed to provide full electrical
compliance with ISO 7816-3, EMV 4.0 (EMV2000) and
NDS specifications.
Interfacing with the system controller is done through a
control bus, composed of digital inputs to control the
interface, and one interrupt output to inform the system
controller of the card presence and faults.
The card clock can be generated by an on-chip oscillator
using an external crystal or by connection to a clock
signal.
The 73S8024RN incorporates an ISO 7816-3
activation/deactivation sequencer that controls the card
signals. Level-shifters drive the card signals with the
selected card voltage (3V or 5V), coming from an internal
Low Drop-Out (LDO) voltage regulator. This LDO
regulator is powered by a dedicated power supply input
V
PC
. Digital circuitry is separately powered by a digital
power supply V
DD
.
With its embedded LDO regulator, the 73S8024RN is a
cost effective solution for any application where a 5V
(typically -5% +10%) power supply is available.
Hardware support for auxiliary I/O lines, C4 / C8 contacts,
is provided*.
Emergency card deactivation is initiated upon card
extraction or upon any fault generated by the protection
circuitry. The fault can be a card over-current, a V
DD
(digital power supply)**, a V
PC
(regulator power supply), a
V
CC
(card power supply) or an over-heating fault.
The card over-current circuitry is a true current detection
function, as opposed to V
CC
voltage drop detection, as
usually implemented in ICC interface ICs.
The V
DD
voltage fault has a threshold voltage that can be
adjusted with an external resistor or resistor network. It
allows automated card deactivation at a customized V
DD
voltage threshold value. It can be used, for instance, to
match the system controller operating voltage range.
•
•
•
•
•
FEATURES
•
APPLICATIONS
•
•
•
Set-Top-Box Conditional Access and Pay-per-
View
Point of Sales and Transaction Terminals
Control Access and Identification
•
* Pins/functions not available on 20-pin QFN package.
** User V
DD_FLT
threshold configuration not available on
20-pin QFN package.
•
•
•
Rev. 2
1
73S8024RN Data Sheet
FUNCTIONAL DIAGRAM
VDD
21 [20] {12}
VDDF_ADJ
18 [17]
NC
5 [2,9,16,25,32]
VPC
6
6 [3] {2}
DS_8024RN_020
V
PC
FAULT
{13} [21] 22
GND
DIGITAL POWER SUPPLY
VDD VOLTAGE SUPERVISOR
VOLTAGE REFERENCE
V
DD
FAULT
V
CC
FAULT
I
CC
FAULT
{10} [18] 19
CMDVCC
{11} [19] 20
RSTIN
{20} [31] 3
5V/3V
{14} [22] 23
OFF
{18} [29] 1
CLKDIV1
{19} [30] 2
CLKDIV2
{15} [23] 24
XTALIN
{16} [24] 25
XTALOUT
[4] 7
CLKSTOP
[5] 8
CLKLEV
{17} [26] 26
I/OUC
[27]
AUX1UC
27
[28]
AUX2UC
28
Int_Clk
DIGITAL
CIRCUITRY
&
FAULT LOGIC
R-C
OSC.
LDO
REGULATOR
&
VOLTAGE
SUPERVISORS
4 [1] {1}
GND
14 [12] {6}
GND
17 [15] {9}
VCC
ICC RESET
BUFFER
16 [14] {8}
RST
ISO-7816
SEQUENCER
XTAL
OSC
CLOCK
GENERATION
ICC CLOCK
BUFFER
15 [13] {7}
CLK
10 [7] {4}
PRES
9 [6] {3}
PRES
OVER
TEMP
TEMP FAULT
11 [8] {5}
I/O
ICC I/O BUFFERS
13 [11]
AUX1
12 [10]
AUX2
Pin numbers reference the 28SO package.
[Pin numbers] reference the 32QFN package.
{Pin numbers} reference the 20QFN package.
Figure 1: 73S8024RN Block Diagram
2
Rev. 2
DS_8024RN_020
73S8024RN Data Sheet
Table of Contents
1
2
3
4
5
6
7
8
9
10
11
12
Pin Description ...............................................................................................................................5
System Controller Interface ...........................................................................................................7
Power Supply and Voltage Supervision ........................................................................................8
Card Power Supply ........................................................................................................................9
Over-Temperature Monitor.............................................................................................................9
On-Chip Oscillator and Card Clock ...............................................................................................9
Activation Sequence ....................................................................................................................10
Deactivation Sequence ................................................................................................................12
OFF
and Fault Detection ..............................................................................................................13
I/O Circuitry and Timing ...............................................................................................................13
Typical Application Schematic ....................................................................................................15
Electrical Specification ................................................................................................................16
12.1 Absolute Maximum Ratings ....................................................................................................16
12.2 Recommended Operating Conditions .....................................................................................16
12.3 Package Thermal Parameters ................................................................................................16
12.4 Smart Card Interface Requirements........................................................................................17
12.5 Characteristics: Digital Signals................................................................................................19
12.6 DC Characteristics..................................................................................................................20
12.7 Voltage / Temperature Fault Detection Circuits .......................................................................20
Mechanical Drawing (20QFN) ......................................................................................................21
Package Pin Designation (20QFN)...............................................................................................22
Mechanical Drawing (32QFN) ......................................................................................................23
Package Pin Designation (32QFN)...............................................................................................24
Mechanical Drawing (SO).............................................................................................................25
Package Pin Designation (SO).....................................................................................................25
Ordering Information....................................................................................................................26
Related Documentation................................................................................................................26
Contact Information .....................................................................................................................26
13
14
15
16
17
18
19
20
21
Revision History ...................................................................................................................................27
Rev. 2
3
73S8024RN Data Sheet
DS_8024RN_020
Figures
Figure 1: 73S8024RN Block Diagram ...................................................................................................... 2
Figure 2: Activation Sequence – RSTIN Low When
CMDVCC
Goes Low .............................................. 10
Figure 3: Activation Sequence – RSTIN High When
CMDVCCB
Goes Low ........................................... 11
Figure 4: Deactivation Sequence ........................................................................................................... 12
Figure 5: Timing Diagram – Management of the Interrupt Line
OFF
....................................................... 13
Figure 6: I/O and I/OUC State Diagram ................................................................................................. 14
Figure 7: I/O – I/OUC Delays Timing Diagram ....................................................................................... 14
Figure 8: 73S8024RN – Typical Application Schematic.......................................................................... 15
Figure 9: 20QFN Mechanical Drawing ................................................................................................... 21
Figure 10: 20QFN Pin Out ..................................................................................................................... 22
Figure 11: 32QFN Mechanical Drawing ................................................................................................. 23
Figure 12: 32QFN Pin Out ..................................................................................................................... 24
Tables
Table 1: Choice of V
CC
Pin Capacitor....................................................................................................... 9
Table 2: Card Clock Frequency ............................................................................................................... 9
4
Rev. 2
DS_8024RN_020
73S8024RN Data Sheet
1
Pin Description
Pin
28SO
11
13
12
16
15
Pin
20QFN
5
–
–
8
7
Pin
Description
32QFN
8
Card I/O: Data signal to/from card. Includes a pull-up
resistor to V
CC.
11
AUX1: Auxiliary data signal to/from card. Includes a
pull-up resistor to V
CC.
10
AUX2: Auxiliary data signal to/from card. Includes a
pull-up resistor to V
CC.
14
Card reset: provides reset (RST) signal to card.
13
Card clock: provides clock signal (CLK) to card. The rate
of this clock is determined by the external crystal
frequency or frequency of the external clock signal applied
on XTALIN and CLKDIV selections.
7
Card Presence switch: active high indicates card is
present. Should be tied to GND when not used, but it
Includes a high-impedance pull-down current source.
6
Card Presence switch: active low indicates card is
present. Should be tied to V
DD
when not used, but it
Includes a high-impedance pull-up current source.
15
Card power supply – logically controlled by sequencer,
output of LDO regulator. Requires an external filter
capacitor to the card GND.
12
Card ground.
CARD INTERFACE
Name
I/O
AUX1
AUX2
RST
CLK
PRES
10
9
17
14
4
3
9
6
PRES
VCC
GND
MISCELLANEOUS INPUTS AND OUTPUTS
Name
XTALIN
XTALOUT
VDDF_ADJ
NC
Pin
28SO
24
25
18
5
Pin
20QFN
15
16
–
–
Pin
32QFN
23
24
17
2, 9,
16, 25,
32
Description
Crystal oscillator input: can either be connected to crystal
or driven as a source for the card clock.
Crystal oscillator output: connected to crystal. Left open
if XTALIN is being used as external clock input.
V
DD
fault threshold adjustment input: this pin can be used
to adjust the V
DDF
values (that controls deactivation of the
card). Must be left open if unused.
Non-connected pin.
POWER SUPPLY AND GROUND
Name
VDD
VPC
GND
GND
Pin
28SO
21
6
4
22
Pin
20QFN
12
2
1
13
Pin
32QFN
20
3
1
21
Description
System interface supply voltage and supply voltage for
internal circuitry.
LDO regulator power supply source.
LDO Regulator ground.
Digital ground.
Rev. 2
5
