Output switching specified for both 50 pF and 250 pF
loads
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Guaranteed latchup protection
High impedance glitch free bus loading during entire
power up and power down
Nondestructive hot insertion capability
Standard Military Drawing (SMD) 5962-9321801
Commercial
74ABT373CSC (Note 1)
74ABT373CSJ (Note 1)
74ABT373CPC
Military
Package
Number
M20B
M20D
N20B
Package Description
20-Lead (0 300 Wide) Molded Small Outline JEDEC
20-Lead (0 300 Wide) Molded Small Outline EIAJ
20-Lead (0 300 Wide) Molded Dual-In-Line
20-Lead Ceramic Dual-In-Line
20-Lead Molded Shrink Small Outline EIAJ Type II
20-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
20-Lead Molded Thin Shrink Small Outline JEDEC
54ABT373J 883
74ABT373CMSA (Note 1)
54ABT373W 883
54ABT373E 883
74ABT373CMTC (Notes 1 2)
Note 2
Contact factory for package availability
J20A
MSA20
W20A
E20A
MTC20
Note 1
Devices also available in 13 reel Use suffix
e
SCX SJX MSAX and MTCX
Connection Diagrams
Pin Assignment
for DIP SOIC SSOP and Flatpak
Pin Assignment
for LCC
Pin Names
D
0
–D
7
LE
OE
O
0
–O
7
Description
Data Inputs
Latch Enable Input
(Active HIGH)
Output Enable Input
(Active LOW)
TRI-STATE Latch
Outputs
TL F 11547 – 2
TL F 11547–1
TRI-STATE is a registered trademark of National Semiconductor Corporation
C
1995 National Semiconductor Corporation
TL F 11547
RRD-B30M115 Printed in U S A
Functional Description
The ’ABT373 contains eight D-type latches with
TRI-STATE output buffers When the Latch Enable (LE) in-
put is HIGH data on the D
n
inputs enters the latches In this
condition the latches are transparent i e a latch output will
change state each time its D input changes When LE is
LOW the latches store the information that was present on
the D inputs a setup time preceding the HIGH-to-LOW tran-
sition of LE The TRI-STATE buffers are controlled by the
Output Enable (OE) input When OE is LOW the buffers are
in the bi-state mode When OE is HIGH the buffers are in
the high impedance mode but this does not interfere with
entering new data into the latches
Truth Table
Inputs
LE
H
H
L
X
OE
L
L
L
H
D
n
H
L
X
X
Output
O
n
H
L
O
n
(no change)
Z
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
Z
e
High Impedance State
Logic Diagram
TL F 11547 – 3
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
Ceramic
Plastic
V
CC
Pin Potential to
Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Any Output
in the Disabled or
Power-Off State
in the HIGH State
Current Applied to Output
in LOW State (Max)
b
65 C to
a
150 C
b
55 C to
a
125 C
b
55 C to
a
175 C
b
55 C to
a
150 C
b
0 5V to
a
7 0V
b
0 5V to
a
7 0V
b
30 mA to
a
5 0 mA
b
150 mA
DC Latchup Source Current
OE Pin
(Across Comm Operating Range) Other Pins
b
500 mA
Over Voltage Latchup (I O)
10V
Note 1
Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired Functional operation under
these conditions is not implied
Note 2
Either voltage limit or current limit is sufficient to protect inputs
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
Commercial
Supply Voltage
Military
Commercial
Minimum Input Edge Rate
Data Input
Enable Input
b
55 C to
a
125 C
b
40 C to
a
85 C
a
4 5V to
a
5 5V
a
4 5V to
a
5 5V
b
0 5V to
a
5 5V
b
0 5V to V
CC
twice the rated I
OL
(mA)
(DV
Dt)
50 mV ns
20 mV ns
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54ABT 74ABT
54ABT
74ABT
54ABT
74ABT
25
20
20
0 55
0 55
5
5
7
b
5
b
5
ABT373
Min
20
08
b
1 2
Typ
Max
Units
V
V
V
V
V
CC
Conditions
Recognized HIGH Signal
Recognized LOW Signal
Min
Min
I
IN
e b
18 mA
I
OH
e b
3 mA
I
OH
e b
24 mA
I
OH
e b
32 mA
I
OL
e
48 mA
I
OL
e
64 mA
V
IN
e
2 7V (Note 2)
V
IN
e
V
CC
V
IN
e
7 0V
V
IN
e
0 5V (Note 2)
V
IN
e
0 0V
I
ID
e
1 9
mA
All Other Pins Grounded
V
OL
I
IH
I
BVI
I
IL
V
ID
I
OZH
I
OZL
I
OS
I
CEX
I
ZZ
I
CCH
I
CCL
I
CCZ
I
CCT
Output LOW Voltage
Input HIGH Current
Input HIGH Current Breakdown Test
Input LOW Current
Input Leakage Test
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Output High Leakage Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
Additional I
CC
Input
V
mA
mA
mA
V
Min
Max
Max
Max
00
4 75
50
b
50
b
100
b
275
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
0
b
5 5V V
OUT
e
2 7V OE
e
2 0V
0
b
5 5V V
OUT
e
0 5V OE
e
2 0V
Max
Max
00
Max
Max
Max
V
OUT
e
0 0V
V
OUT
e
V
CC
V
OUT
e
5 5V All Others GND
All Outputs HIGH
All Outputs LOW
OE
e
V
CC
All Others at V
CC
or GND
V
I
e
V
CC
b
2 1V
Enable Input V
I
e
V
CC
b
2 1V
Data Input V
I
e
V
CC
b
2 1V
All Others at V
CC
or GND
Outputs Open LE
e
V
CC
OE
e
GND (Note 1)
One Bit Toggling 50% Duty Cycle
50
100
50
30
50
Outputs Enabled
Outputs TRI-STATE
Outputs TRI-STATE
No Load
25
25
25
Max
I
CCD
Dynamic I
CC
(Note 2)
0 12
mA
MHz
Max
Note 1
For 8 bits toggling I
CCD
k
0 8 mA MHz
Note 2
Guaranteed but not tested
3
DC Electrical Characteristics
Symbol
V
OLP
V
OLV
V
OHV
V
IHD
V
ILD
Parameter
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
(SOIC Package) (Continued)
Min
Typ
04
b
1 2
b
0 8
Max
08
Units
V
V
V
V
V
CC
50
50
50
50
50
Conditions
C
L
e
50 pF R
L
e
500X
T
A
e
25 C (Note 1)
T
A
e
25 C (Note 1)
T
A
e
25 C (Note 3)
T
A
e
25 C (Note 2)
T
A
e
25 C (Note 2)
Minimum High Level Dynamic Output Voltage
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
25
20
30
17
09
06
V
Note 1
Max number of outputs defined as (n) n
b
1 data inputs are driven 0V to 3V One output at Low Guaranteed but not tested
Note 2
Max number of data inputs (n) switching n
b
1 inputs switching 0V to 3V Input-under-test switching 3V to theshold (V
ILD
) 0V to threshold (V
IHD
)
Guaranteed but not tested
Note 3
Max number of outputs defined as (n) n
b
1 data inputs are driven 0V to 3V One output HIGH Guaranteed but not tested
AC Electrical Characteristics
74ABT
Symbol
Parameter
T
A
e a
25 C
V
CC
e a
5 0V
C
L
e
50 pF
Min
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation Delay
D
n
to O
n
Propagation Delay
LE to O
n
Output Enable Time
Output Disable Time
19
19
20
20
15
15
20
20
Typ
27
28
31
30
31
31
36
34
Max
45
45
50
50
53
53
54
54
54ABT
T
A
e b
55 C to
a
125 C
V
CC
e
4 5V to 5 5V
C
L
e
50 pF
Min
10
10
10
15
10
15
17
10
Max
68
70
77
77
67
72
80
70
74ABT
T
A
e b
40 C to
a
85 C
V
CC
e
4 5V to 5 5V
C
L
e
50 pF
Min
19
19
20
20
15
15
20
20
Max
45
45
50
50
53
53
54
54
ns
ns
ns
ns
Units
AC Operating Requirements
74ABT
Symbol
Parameter
Min
f
toggle
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
w
(H)
Max Toggle
Frequency
Setup Time HIGH
or LOW D
n
to LE
Hold Time HIGH
or LOW D
n
to LE
Pulse Width
LE HIGH
15
15
10
10
30
T
A
e a
25 C
V
CC
e a
5 0V
C
L
e
50 pF
Typ
100
Max
54ABT
T
A
e b
55 C to
a
125 C
V
CC
e
4 5V to 5 5V
C
L
e
50 pF
Min
100
25
25
25
25
33
15
15
10
10
30
Max
74ABT
T
A
e b
40 C to
a
85 C
V
CC
e
4 5V to 5 5V
C
L
e
50 pF
Min
Max
MHz
ns
ns
ns
Units
4
Extended AC Electrical Characteristics
(SOIC package)
74ABT
T
A
e b
40 C to
a
85 C
V
CC
e
4 5V to 5 5V
C
L
e
50 pF
8 Outputs Switching
(Note 4)
Min
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PZL
Propagation Delay
D
n
to O
n
Propagation Delay
LE to O
n
Output Enable Time
Output Disable Time
15
15
15
15
15
15
10
10
Max
52
52
55
55
62
62
55
55
74ABT
T
A
e b
40 C to
a
85 C
V
CC
e
4 5V to 5 5V
C
L
e
250 pF
(Note 5)
Min
20
20
20
20
20
20
(Note 7)
Max
68
68
75
75
80
80
74ABT
T
A
e b
40 C to
a
85 C
V
CC
e
4 5V to 5 5V
C
L
e
250 pF
8 Outputs Switching
(Note 6)
Min
20
20
20
20
20
20
(Note 7)
Max
90
90
95
95
10 5
10 5
ns
ns
ns
ns
Symbol
Parameter
Units
Note 4
This specification is guaranteed but not tested The limits apply to propagation delays for all paths described switching in phase (i e all LOW-to-HIGH
HIGH-to-LOW etc )
Note 5
This specification is guaranteed but not tested The limits represent propagation delay with 250 pF load capacitors in plce of the 50 pF load capacitors in
the standard AC load This specificaiton pertains to single output switching only
Note 6
This specification is guaranteed but not tested The limits represent propagation delays for all paths described switching in phase (i e all LOW-to-HIGH
HIGH-to-LOW etc ) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load
Note 7
The TRI-STATE delay times are dominated by the RC network (500X 250 pF) on the output and has been excluded from the datasheet
Skew
74ABT
T
A
e b
40 C to
a
85 C
V
CC
e
4 5V–5 5V
C
L
e
50 pF
8 Outputs Switching
(Note 3)
Max
t
OSHL
(Note 1)
t
OSLH
(Note 1)
t
PS
(Note 5)
t
OST
(Note 1)
t
PV
(Note 2)
Pin to Pin Skew
HL Transitions
Pin to Pin Skew
LH Transitions
Duty Cycle
LH–HL Skew
Pin to Pin Skew
LH HL Transitions
Device to Device Skew
LH HL Transitions
10
10
14
15
20
74ABT
T
A
e b
40 C to
a
85 C
V
CC
e
4 5V–5 5V
C
L
e
250 pF
8 Outputs Switching
(Note 4)
Max
15
15
35
39
40
ns
ns
ns
ns
ns
Symbol
Parameter
Units
Note 1
Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device The
specification applies to any outputs switching HIGH to LOW (t
OSHL
) LOW to HIGH (t
OSLH
) or any combination switching LOW to HIGH and or HIGH to LOW
(t
OST
) This specification is guaranteed but not tested
Note 2
Propagation delay variation for a given set of conditions (i e temperature and V
CC
) from device to device This specification is guaranteed but not tested
Note 3
This specification is guaranteed but not tested The limits apply to propagation delays for all paths described switching in phase (i e all LOW-to-HIGH
HIGH-to-LOW etc )
Note 4
This specification is guaranteed but not tested The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in
the standard AC load
Note 5
This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin It is measured across all the
outputs (drivers) on the same chip the worst (largest delta) number is the guaranteed specification This specification is guaranteed but not tested
WindowsCE
