74AC138
3 TO 8 LINE DECODER (INVERTING)
s
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
= 4.5ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 4µA(MAX.) at T
A
=25°C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
50Ω TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 6V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 138
IMPROVED LATCH-UP IMMUNITY
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
DIP
SOP
TSSOP
TUBE
74AC138B
74AC138M
DESCRIPTION
The 74AC138 is an advanced high-speed CMOS
3 TO 8 LINE DECODER (INVERTING) fabricated
with sub-micron silicon gate and double-layer
metal wiring C
2
MOS tecnology.
If the device is enabled, 3 binary select inputs (A,
B, and C) determine which one of the outputs will
go low. If enable input G1 is held low or either G2A
PIN CONNECTION AND IEC LOGIC SYMBOLS
O
so
b
te
le
ro
P
uc
d
s)
t(
so
b
-O
or G2B is held high, the decoding function is
inhibited and all the 8 outputs go to high.
Tree enable inputs are provided to ease cascade
connection and application of address decoders
for memory systems.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
P
te
le
od
r
s)
t(
uc
T&R
74AC138MTR
74AC138TTR
April 2001
1/10
74AC138
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
1, 2, 3
4, 5
6
15, 14, 13,
12, 11, 10, 9,
7
8
16
SYMBOL
A, B, C
G2A, G2B
G1
Y0 to Y7
NAME AND FUNCTION
Address Inputs
Enable Inputs
Enable Input
Outputs
GND
V
CC
Ground (0V)
Positive Supply Voltage
TRUTH TABLE
INPUTS
OUTPUTS
ENABLE
G2B
X
X
H
L
L
L
L
L
L
L
L
G2A
X
H
X
L
L
L
L
L
L
L
L
G1
L
X
X
H
H
H
H
H
H
H
H
C
X
X
X
L
L
L
L
H
H
H
H
SELECT
B
X
X
X
L
L
H
H
L
L
H
H
A
X
X
X
L
H
L
H
L
H
L
H
Y0
H
H
H
L
H
H
H
H
H
H
H
Y1
H
H
H
H
L
H
H
H
H
H
H
Y2
H
H
H
H
H
L
H
H
H
H
H
Y3
H
H
H
H
H
H
L
H
H
H
H
Y4
H
H
H
H
H
H
H
L
H
H
H
Y5
H
H
H
H
H
H
H
H
L
H
H
X : Don’t Care
LOGIC DIAGRAM
O
so
b
te
le
ro
P
uc
d
s)
t(
so
b
-O
P
te
le
od
r
s)
t(
uc
Y6
H
H
H
H
H
H
H
H
H
L
H
Y7
H
H
H
H
H
H
H
H
H
H
L
This logic diagram has not be used to estimate propagation delays
2/10
74AC138
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
Parameter
Value
-0.5 to +7
-0.5 to V
CC
+ 0.5
-0.5 to V
CC
+ 0.5
±
20
±
20
±
50
±
400
-65 to +150
300
Unit
V
V
V
mA
mA
mA
mA
°C
°C
I
CC
or I
GND
DC V
CC
or Ground Current
T
stg
Storage Temperature
T
L
Lead Temperature (10 sec)
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
I
V
O
T
op
dt/dv
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time V
CC
= 3.0, 4.5 or 5.5V (note 1)
Parameter
Value
2 to 6
0 to V
CC
1) V
IN
from 30% to 70% of V
CC
O
so
b
te
le
ro
P
uc
d
s)
t(
so
b
-O
te
le
r
P
0 to V
CC
8
-55 to 125
od
s)
t(
uc
Unit
V
V
V
°C
ns/V
3/10
74AC138
DC SPECIFICATIONS
Test Condition
Symbol
Parameter
V
CC
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
V
OL
Low Level Output
Voltage
3.0
4.5
5.5
3.0
4.5
5.5
I
I
I
CC
I
OLD
I
OHD
Input Leakage
Current
Quiescent Supply
Current
Dynamic Output
Current (note 1, 2)
5.5
5.5
5.5
V
O
= 0.1 V or
V
CC
-0.1V
V
O
= 0.1 V or
V
CC
-0.1V
I
O
=-50
µA
I
O
=-50
µA
I
O
=-50
µA
I
O
=-12 mA
I
O
=-24 mA
I
O
=-24 mA
I
O
=50
µA
I
O
=50
µA
I
O
=50
µA
I
O
=12 mA
I
O
=24 mA
I
O
=24 mA
V
I
= V
CC
or GND
V
I
= V
CC
or GND
2.9
4.4
5.4
2.56
3.86
4.86
0.002
0.001
0.001
0.1
0.1
0.1
0.36
0.36
0.36
T
A
= 25°C
Min.
2.1
3.15
3.85
Typ.
1.5
2.25
2.75
1.5
2.25
2.75
2.99
4.49
5.49
Max.
Value
-40 to 85°C
Min.
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.46
3.76
4.76
0.1
0.9
1.35
1.65
2.9
4.4
5.4
2.4
V
Max.
-55 to 125°C
Min.
2.1
3.15
3.85
0.9
1.35
1.65
Max.
V
Unit
V
IH
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
V
IL
V
V
OH
V
OLD
= 1.65 V max
V
OHD
= 3.85 V min
1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50Ω
O
so
b
te
le
ro
P
uc
d
s)
t(
b
-O
so
P
te
le
±
0.1
4
od
r
0.1
0.1
0.44
0.44
0.44
±
1
40
75
-75
s)
t(
uc
3.7
4.7
0.1
0.1
0.1
0.5
0.5
0.5
±
1
80
50
-50
µA
µA
mA
mA
V
4/10
74AC138
AC ELECTRICAL CHARACTERISTICS
(C
L
= 50 pF, R
L
= 500
Ω,
Input t
r
= t
f
= 3ns)
Test Condition
Symbol
Parameter
V
CC
(V)
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
T
A
= 25°C
Min.
1.5
1.5
1.5
1.5
1.5
1.5
Typ.
5.5
4.5
6.0
4.5
5.5
4.5
Max.
10.5
9.0
10.5
11.0
10.5
9.0
Value
-40 to 85°C
Min.
1.5
1.5
1.5
1.5
1.5
1.5
Max.
14.0
10.0
14.0
10.0
12.7
10.0
-55 to 125°C
Min.
1.5
1.5
1.5
1.5
1.5
1.5
Max.
15.4
11.0
15.4
11.0
14.0
10.0
ns
ns
ns
Unit
t
PLH
t
PHL
Propagation Delay
Time
A, B, C to Y
t
PLH
t
PHL
Propagation Delay
Time
G1 to Y
t
PLH
t
PHL
Propagation Delay
Time
G2A or G2B to Y
(*) Voltage range is 3.3V
±
0.3V
(**) Voltage range is 5.0V
±
0.5V
CAPACITIVE CHARACTERISTICS
Test Condition
Symbol
Parameter
V
CC
(V)
5.0
5.0
f
IN
= 10MHz
60
T
A
= 25°C
Min.
Typ.
4
Max.
Value
-40 to 85°C
Min.
C
IN
C
PD
Input Capacitance
Power Dissipation
Capacitance
(note 1)
1) C
PD
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/n (per circuit)
TEST CIRCUIT
O
so
b
te
le
ro
P
uc
d
s)
t(
so
b
-O
P
te
le
od
r
Max.
-55 to 125°C
Min.
Max.
s)
t(
uc
Unit
pF
pF
C
L
= 50pF or equivalent (includes jig and probe capacitance)
R
L
= R
1
= 500Ω or equivalent
R
T
= Z
OUT
of pulse generator (typically 50Ω)
5/10
