74ACT533 Octal Transparent Latch with 3-STATE Outputs
August 1999
Revised March 2005
74ACT533
Octal Transparent Latch with 3-STATE Outputs
General Description
The ACT533 consists of eight latches with 3-STATE out-
puts for bus organized system applications. The flip-flops
appear transparent to the data when Latch Enable (LE) is
HIGH. When LE is low, the data satisfying the input timing
requirements is latched. Data appears on the bus when the
Output Enable (OE) is LOW. When OE is HIGH, the bus
output is in the high impedance state.
Features
s
I
CC
and I
OZ
reduced by 50%
s
Eight latches in a single package
s
3-STATE outputs drive bus lines or buffer memory
address registers
s
Outputs source/sink 24 mA
s
Inverted version of the ACT373
s
TTL-compatible inputs
Ordering Code:
Order Number
74ACT533SC
74ACT533MTC
74ACT533PC
Package Number
M20B
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D
0
–D
7
LE
OE
O
0
–O
7
Description
Data Inputs
Latch Enable Input
Output Enable Input
3-STATE Latch Outputs
FACT
¥
is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS500311
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74ACT533
Functional Description
The ACT533 contains eight D-type latches with 3-STATE
standard outputs. When the Latch Enable (LE) input is
HIGH, data on the D
n
inputs enters the latches. In this con-
dition the latches are transparent, i.e., a latch output will
change state each time its D input changes. When LE is
LOW, the latches store the information that was present on
the D inputs at setup time preceding the HIGH-to-LOW
transition of LE. The 3-STATE standard outputs are con-
trolled by the Output Enable (OE) input. When OE is LOW,
the standard outputs are in the 2-state mode. When OE is
HIGH, the standard outputs are in the high impedance
mode but this does not interfere with entering new data into
the latches.
Truth Table
Inputs
LE
X
H
H
L
H
L
Z
X
O
0
Outputs
D
n
X
L
H
X
O
n
Z
H
L
O
0
OE
H
L
L
L
HIGH Voltage Level
LOW Voltage Level
High Impedance
Immaterial
Previous O
0
before HIGH-to-LOW transition of Latch Enable
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
74ACT533
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
V
I
0.5V to
7.0V
20 mA
20 mA
0.5V to V
CC
0.5V
20 mA
20 mA
0.5V to V
CC
0.5V
r
50 mA
r
50 mA
65
q
C to
150
q
C
r
300 mA
140
q
C
Recommended Operating
Conditions
Supply Voltage (V
CC
)
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Minimum Input Edge Rate
'
V/
'
t
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
125 mV/ns
4.5V to 5.5V
0V to V
CC
0V to V
CC
0.5V
V
CC
0.5V
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
V
O
40
q
C to
85
q
C
0.5V
V
CC
0.5V
DC Output Voltage (V
O
)
DC Output Source
or Sink Current (I
O
)
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
Storage Temperature (T
STG
)
DC Latchup Source
or Sink Current
Junction Temperature (T
J
)
PDIP
Note 1:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT
¥
circuits outside databook specifications.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Parameter
Minimum HIGH Level
Input Voltage
Maximum LOW Level
Input Voltage
Minimum HIGH Level
Output Voltage
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
V
OL
Maximum LOW Level
Output Voltage
4.5
5.5
4.5
5.5
I
IN
I
OZ
I
CCT
I
OLD
I
OHD
I
CC
Maximum Input
Leakage Current
Maximum 3-STATE
Leakage Current
Maximum
I
CC
/Input
Minimum Dynamic
Output Current (Note 3)
Maximum Quiescent
Supply Current
5.5
5.5
5.5
4.0
75
mA
mA
V
OLD
V
OHD
V
IN
or GND
1.65V Max
3.85V Min
V
CC
5.5
5.5
0.6
5.5
0.001
0.001
T
A
Typ
1.5
1.5
1.5
1.5
4.49
5.49
2.0
2.0
0.8
0.8
4.4
5.4
3.86
4.86
0.1
0.1
0.36
0.36
25
q
C
T
A
40
q
C to
85
q
C
2.0
2.0
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
Guaranteed Limits
Units
V
V
V
V
OUT
V
OUT
I
OUT
V
IN
V
I
OH
I
OH
V
I
OUT
V
IN
V
I
OL
I
OL
V
I
V
I
V
O
Conditions
0.1V
0.1V
or V
CC
0.1V
or V
CC
0.1V
50
P
A
V
IL
or V
IH
24 mA
24 mA (Note 2)
50
P
A
V
IL
or V
IH
24 mA
24 mA (Note 2)
V
CC
, GND
V
IL
, V
IH
V
CC
, GND
V
I
V
CC
2.1V
r
0.1
r
1.0
P
A
r
0.25
r
2.5
1.5
P
A
mA
75
40.0
P
A
Note 2:
All outputs loaded; thresholds on input associated with output under test.
Note 3:
Maximum test duration 2.0 ms, one output loaded at a time.
3
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74ACT533
AC Electrical Characteristics
V
CC
Symbol
Parameter
(V)
(Note 4)
t
PHL
t
PLH
t
PHL
t
PLH
t
PZL
, t
PZH
t
PHZ
, t
PLZ
Propagation Delay
D
n
to O
n
Propagation Delay
LE to O
n
Output Enable Time
Output Disable Time
5.0
5.0
2.0
1.0
7.0
8.0
9.0
10.0
2.0
1.0
9.5
10.5
ns
ns
5.0
2.5
7.0
9.0
2.5
9.5
ns
5.0
Min
2.0
T
A
C
L
25
q
C
50 pF
Typ
6.0
Max
8.0
T
A
40
q
C to
85
q
C
C
L
Min
2.0
50 pF
Max
8.5
ns
Units
Note 4:
Voltage Range 5.0 is 5.0V
r
0.5V.
AC Operating Requirements
V
CC
Symbol
Parameter
(V)
(Note 5)
t
S
t
H
t
W
Setup Time, HIGH or LOW
D
n
to LE
Hold Time, HIGH or LOW
D
n
to LE
LE Pulse Width, HIGH
5.0
2.0
4.0
4.0
ns
Note 5:
Voltage Range 5.0 is 5.0V
r
0.5V.
T
A
C
L
Typ
0
0
25
q
C
50 pF
T
A
40
q
C to
85
q
C
C
L
50 pF
Units
Guaranteed Minimum
3.0
1.5
3.0
1.5
ns
ns
5.0
5.0
Capacitance
Symbol
C
IN
C
PD
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ
4.5
40
Units
pF
pF
V
CC
V
CC
OPEN
5.0V
Conditions
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4
74ACT533
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
5
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