74AHC164-Q100;
74AHCT164-Q100
8-bit serial-in/parallel-out shift register
Rev. 1 — 5 July 2013
Product data sheet
1. General description
The 74AHC164-Q100; 74AHCT164-Q100 shift register is a high-speed Si-gate CMOS
device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in
compliance with JEDEC standard No. 7A.
The 74AHC164-Q100; 74AHCT164-Q100 input signals are 8-bit serial through one of two
inputs (DSA or DSB). Either input can be used as an active HIGH enable for data entry
through the other input. Both inputs must be connected together or an unused input must
be tied HIGH.
Data shifts one place to the right on each LOW-to-HIGH transition of the clock input (CP).
It enters into output Q0, which is a logical AND of the two data inputs (DSA and DSB).
These data inputs existed one set-up time, prior to the rising clock edge.
A LOW-level on the master reset (MR) input overrides all other inputs and clears the
register asynchronously, forcing all outputs LOW.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Balanced propagation delays
All inputs have Schmitt-trigger actions
Inputs accept voltages higher than V
CC
Input levels:
For 74AHC164-Q100: CMOS level
For 74AHCT164-Q100: TTL level
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
Multiple package options
NXP Semiconductors
74AHC164-Q100; 74AHCT164-Q100
8-bit serial-in/parallel-out shift register
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74AHC164-Q100
74AHC164D-Q100
74AHC164PW-Q100
74AHC164BQ-Q100
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
SO14
TSSOP14
DHVQFN14
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin shrink small outline package;
14 leads; body width 4.4 mm
SOT108-1
SOT402-1
Description
Version
Type number
plastic dual in-line compatible thermal enhanced SOT762-1
very thin quad flat package; no leads;
14 terminals; body 2.5
3
0.85 mm
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin shrink small outline package;
14 leads; body width 4.4 mm
SOT108-1
SOT402-1
74AHCT164-Q100
74AHCT164D-Q100
40 C
to +125
C
SO14
TSSOP14
DHVQFN14
74AHCT164PW-Q100
40 C
to +125
C
74AHCT164BQ-Q100
40 C
to +125
C
plastic dual in-line compatible thermal enhanced SOT762-1
very thin quad flat package; no leads;
14 terminals; body 2.5
3
0.85 mm
4. Functional diagram
DSA
DSB
CP
MR
1
2
8
9
3
4
5
6
10
11
12
13
8-BIT SERIAL−IN/PARALLEL−OUT
SHIFT REGISTER
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
001aac425
Fig 1.
Functional diagram
74AHC_AHCT164_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 5 July 2013
2 of 19
NXP Semiconductors
74AHC164-Q100; 74AHCT164-Q100
8-bit serial-in/parallel-out shift register
SRG8
8
9
1
2
C1/
R
3
4
&
1D
DSA
DSB
3
1
2
4
5
6
10
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
001aac424
5
6
10
11
12
13
CP
MR
8
9
11
12
13
001aac423
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
DSA
D
DSB
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
CP
FF1
R
D
CP
FF2
R
D
CP
FF3
R
D
CP
FF4
R
D
CP
FF5
R
D
CP
FF6
R
D
CP
FF7
R
D
CP
FF8
R
D
CP
MR
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
001aac616
Fig 4.
Logic diagram
74AHC_AHCT164_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 5 July 2013
3 of 19
NXP Semiconductors
74AHC164-Q100; 74AHCT164-Q100
8-bit serial-in/parallel-out shift register
5. Pinning information
5.1 Pinning
(1) The die substrate is attached to this pad using
conductive die attach material. It cannot be used as a
supply pin or input.
Fig 5.
Pin configuration SO14 and TSSOP14
Fig 6.
Pin configuration DHVQFN14
5.2 Pin description
Table 2.
Symbol
DSA
DSB
Q0
Q1
Q2
Q3
GND
CP
MR
Q4
Q5
Q6
Q7
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
serial data input A
serial data input B
output 0
output 1
output 2
output 3
ground (0 V)
clock input (LOW-to-HIGH edge-triggered)
master reset input (active LOW)
output 4
output 5
output 6
output 7
supply voltage
74AHC_AHCT164_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 5 July 2013
4 of 19
NXP Semiconductors
74AHC164-Q100; 74AHCT164-Q100
8-bit serial-in/parallel-out shift register
6. Functional description
Table 3.
Function table
[1]
Control
MR
Reset (clear)
Shift
L
H
CP
X
Input
DSA
X
l
l
h
h
[1]
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
= LOW-to-HIGH transition;
X = don’t care;
q = lower case letter indicates the state of the referenced input one set-up time prior to the LOW-to-HIGH transition.
Operating mode
Output
DSB
X
l
h
l
h
Q0
L
L
L
L
H
Q1 to Q7
L to L
q0 to q6
q0 to q6
q0 to q6
q0 to q6
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
Min
0.5
0.5
Max
+7.0
+7.0
-
+20
+25
+75
-
+150
500
Unit
V
V
mA
mA
mA
mA
mA
C
mW
V
I
<
0.5
V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
0.5
V to (V
CC
+ 0.5 V)
[1]
[1]
20
20
25
-
75
65
T
amb
=
40 C
to +125
C
[2]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SO14 packages: above 70
C
the value of P
tot
derates linearly at 8 mW/K.
For TSSOP14 packages: above 60
C
the value of P
tot
derates linearly at 5.5 mW/K.
For DHVQFN14 packages: above 60
C
the value of P
tot
derates linearly at 4.5 mW/K.
74AHC_AHCT164_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 5 July 2013
5 of 19
