74AHC273; 74AHCT273
Octal D-type flip-flop with reset; positive-edge trigger
Rev. 03 — 13 May 2008
Product data sheet
1. General description
The 74AHC273; 74AHCT273 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7-A.
The 74AHC273; 74AHCT273 has eight edge-triggered, D-type flip-flops with individual D
inputs and Q outputs.
The common clock (CP) and master reset (MR) inputs, load and reset (clear) all flip-flops
simultaneously.
The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is
transferred to the corresponding output (Qn) of the flip-flop.
All outputs will be forced LOW, independent of clock or data inputs, by a LOW on the MR
input.
The device is useful for applications where only the true output is required and the clock
and master reset are common to all storage elements.
2. Features
I
I
I
I
I
I
Balanced propagation delays
All inputs have Schmitt-trigger actions
Inputs accept voltages higher than V
CC
Ideal buffer for MOS microcontroller or memory
Common clock and master reset
Related product versions:
N
74AHC377; 74AHCT377 for clock enable version
N
74AHC373; 74AHCT373 for transparent latch version
N
74AHC374; 74AHCT374 for 3-state version
Input levels:
N
For 74AHC273: CMOS level
N
For 74AHCT273: TTL level
ESD protection:
N
HBM EIA/JESD22-A114E exceeds 2000 V
N
MM EIA/JESD22-A115-A exceeds 200 V
N
CDM EIA/JESD22-C101C exceeds 1000 V
Multiple package options
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C
I
I
I
I
NXP Semiconductors
74AHC273; 74AHCT273
Octal D-type flip-flop with reset; positive-edge trigger
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74AHC273
74AHC273D
74AHC273PW
74AHC273BQ
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
SO20
TSSOP20
DHVQFN20
plastic small outline package; 20 leads;
body width 7.5 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT163-1
SOT360-1
Description
Version
Type number
plastic dual in-line compatible thermal enhanced very SOT764-1
thin quad flat package; no leads; 20 terminals; body
2.5
×
4.5
×
0.85 mm
plastic small outline package; 20 leads;
body width 7.5 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT163-1
SOT360-1
74AHCT273
74AHCT273D
74AHCT273PW
74AHCT273BQ
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
SO20
TSSOP20
DHVQFN20
plastic dual in-line compatible thermal enhanced very SOT764-1
thin quad flat package; no leads; 20 terminals; body
2.5
×
4.5
×
0.85 mm
4. Functional diagram
CP
MR
11
3
4
7
8
13
14
17
18
CP
D0
D1
D2
D3
D4
D5
D6
D7
MR
1
mna763
11
1
C1
R
D0
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
D1
D2
D3
D4
D5
D6
D7
3
4
7
8
13
14
17
18
1D
2
5
6
9
12
15
16
19
mna764
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74AHC_AHCT273_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 13 May 2008
2 of 18
NXP Semiconductors
74AHC273; 74AHCT273
Octal D-type flip-flop with reset; positive-edge trigger
D0
D1
D2
D3
D
Q
D
Q
D
Q
D
Q
CP
FF1
R
D
CP
CP
FF2
R
D
CP
FF3
R
D
CP
FF4
R
D
MR
Q0
D4
D5
Q1
D6
Q2
D7
Q3
D
Q
D
Q
D
Q
D
Q
CP
FF5
R
D
CP
FF6
R
D
CP
FF7
R
D
CP
FF8
R
D
Q4
Q5
Q6
Q7
001aae056
Fig 3.
Logic diagram
3
4
7
8
13
14
17
18
1
11
D0
D1
D2
D3
D4
D5
D6
D7
MR
CP
FF1
TO
FF8
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
001aae055
Fig 4.
Functional diagram
74AHC_AHCT273_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 13 May 2008
3 of 18
NXP Semiconductors
74AHC273; 74AHCT273
Octal D-type flip-flop with reset; positive-edge trigger
5. Pinning information
5.1 Pinning
74AHC273
74AHCT273
terminal 1
index area
20 V
CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
GND
(1)
13 D4
12 Q4
GND 10
CP 11
MR
2
3
4
5
6
7
8
9
1
Q0
D0
MR
Q0
D0
D1
Q1
Q2
D2
D3
Q3
1
2
3
4
5
6
7
8
9
20 V
CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 CP
001aai066
74AHC273
74AHCT273
D1
Q1
Q2
D2
D3
Q3
GND 10
001aai067
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as a
supply pin or input.
Fig 5.
Pin configuration SO20 and TSSOP20
Fig 6.
Pin configuration DHVQFN20
5.2 Pin description
Table 2.
Symbol
MR
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
CP
Q4
D4
D5
Q5
Q6
74AHC_AHCT273_3
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
master reset input (active LOW)
flip-flop output
data input
data input
flip-flop output
flip-flop output
data input
data input
flip-flop output
ground (0 V)
clock input (LOW-to-HIGH edge-triggered)
flip-flop output
data input
data input
flip-flop output
flip-flop output
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 13 May 2008
4 of 18
NXP Semiconductors
74AHC273; 74AHCT273
Octal D-type flip-flop with reset; positive-edge trigger
Table 2.
Symbol
D6
D7
Q7
V
CC
Pin description
…continued
Pin
17
18
19
20
Description
data input
data input
flip-flop output
supply voltage
6. Functional description
Table 3.
Function table
[1]
Control
MR
Reset (clear)
Load ‘1’
Load ‘0’
[1]
Operating mode
Input
CP
X
↑
↑
Dn
X
h
l
Output
Qn
L
H
L
L
H
H
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
↑
= LOW-to-HIGH;
X = don’t care.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
Min
−0.5
−0.5
Max
+7.0
+7.0
-
+20
+25
+75
-
+150
500
Unit
V
V
mA
mA
mA
mA
mA
°C
mW
V
I
<
−0.5
V
V
O
<
−0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
−0.5
V to (V
CC
+ 0.5 V)
[1]
[1]
−20
−20
−25
-
−75
−65
T
amb
=
−40 °C
to +125
°C
[2]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SO20 packages: above 70
°C
the value of P
tot
derates linearly at 8 mW/K.
For TSSOP20 packages: above 60
°C
the value of P
tot
derates linearly at 5.5 mW/K.
For DHVQFN20 packages: above 60
°C
the value of P
tot
derates linearly at 4.5 mW/K.
74AHC_AHCT273_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 13 May 2008
5 of 18
