74ALVC00-Q100
Quad 2-input NAND gate
Rev. 1 — 16 May 2014
Product data sheet
1. General description
The 74ALVC00-Q100 is a quad 2-input NAND gate.
Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 3) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 3)
Specified from
40 C
to +85
C
Wide supply voltage range from 1.65 V to 3.6 V
3.6 V tolerant inputs/outputs
CMOS low power consumption
Direct interface with TTL levels (2.7 V to 3.6 V)
Power-down mode
Latch-up performance exceeds 250 mA
Complies with JEDEC standards:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74ALVC00D-Q100
40 C
to +85
C
Name
SO14
TSSOP14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT402-1
Type number
74ALVC00PW-Q100
40 C
to +85
C
74ALVC00BQ-Q100
40 C
to +85
C
DHVQFN14 plastic dual in-line compatible thermal enhanced
SOT762-1
very thin quad flat package; no leads; 14 terminals;
body 2.5
3
0.85 mm
NXP Semiconductors
74ALVC00-Q100
Quad 2-input NAND gate
4. Functional diagram
1
2
4
5
9
10
12
13
&
3
&
6
&
8
A
&
mna246
11
B
Y
mna211
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram for one gate
5. Pinning information
5.1 Pinning
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4.
Pin configuration SO14 and TSSOP14
Fig 5.
Pin configuration DHVQFN14
5.2 Pin description
Table 2.
Symbol
1A to 4A
1B to 4B
1Y to 4Y
GND
V
CC
74ALVC00-Q100
Pin description
Pin
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8, 11
7
14
Description
data input
data input
data output
ground (0 V)
supply voltage
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 16 May 2014
2 of 14
NXP Semiconductors
74ALVC00-Q100
Quad 2-input NAND gate
6. Functional description
Table 3.
Input
nA
L
X
H
[1]
Function selection
[1]
Output
nB
X
L
H
nY
H
H
L
H = HIGH voltage level; L = LOW voltage level; X = don’t care
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
V
O
> V
CC
or V
O
< 0 V
output HIGH or LOW state
output 3-state
power-down mode, V
CC
= 0 V
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
[2]
[1] [2]
Conditions
V
I
< 0 V
Min
0.5
50
0.5
-
0.5
0.5
0.5
-
-
100
65
Max
+4.6
-
+4.6
50
V
CC
+ 0.5
+4.6
+4.6
50
100
-
+150
500
Unit
V
mA
V
mA
V
V
V
mA
mA
mA
C
mW
output current
supply current
ground current
storage temperature
total power dissipation
V
O
= 0 V to V
CC
T
amb
=
40 C
to +85
C
[3]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
When V
CC
= 0 V (power-down mode), the output voltage can be 3.6 V in normal operation.
For SO14 packages: above 70
C
derate linearly with 8 mW/K.
For TSSOP14 packages: above 60
C
derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60
C
derate linearly with 4.5 mW/K.
74ALVC00-Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 16 May 2014
3 of 14
NXP Semiconductors
74ALVC00-Q100
Quad 2-input NAND gate
8. Recommended operating conditions
Table 5.
Symbol
V
CC
V
I
V
O
Recommended operating conditions
Parameter
supply voltage
input voltage
output voltage
output HIGH or LOW state
output 3-state
power-down mode; V
CC
= 0 V
T
amb
t/V
ambient temperature
input transition rise and fall rate
in free air
V
CC
= 1.65 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
Conditions
Min
1.65
0
0
0
0
40
0
0
Max
3.6
3.6
V
CC
3.6
3.6
+85
20
10
Unit
V
V
V
V
V
C
ns/V
ns/V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
HIGH-level input voltage
Conditions
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
IL
LOW-level input voltage
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
OH
HIGH-level output voltage
V
I
= V
IH
or V
IL
I
O
=
100 A;
V
CC
= 1.65 V to 3.6 V
I
O
=
6
mA; V
CC
= 1.65 V
I
O
=
12
mA; V
CC
= 2.3 V
I
O
=
18
mA; V
CC
= 2.3 V
I
O
=
12
mA; V
CC
= 2.7 V
I
O
=
18
mA; V
CC
= 3.0 V
I
O
=
24
mA; V
CC
= 3.0 V
V
OL
LOW-level output voltage
V
I
= V
IH
or V
IL
I
O
= 100
A;
V
CC
= 1.65 V to 3.6 V
I
O
= 6 mA; V
CC
= 1.65 V
I
O
= 12 mA; V
CC
= 2.3 V
I
O
= 18 mA; V
CC
= 2.3 V
I
O
= 12 mA; V
CC
= 2.7 V
I
O
= 18 mA; V
CC
= 3.0 V
I
O
= 24 mA; V
CC
= 3.0 V
I
I
I
OFF
74ALVC00-Q100
T
amb
=
40 C
to +85
C
Min
0.65
V
CC
1.7
2.0
-
-
-
V
CC
0.2
1.25
1.8
1.7
2.2
2.4
2.2
-
-
-
-
-
-
-
-
-
Typ
[1]
-
-
-
-
-
-
-
1.51
2.10
2.01
2.53
2.76
2.68
-
0.11
0.17
0.25
0.16
0.23
0.30
0.1
0.1
Max
-
-
-
0.7
0.8
-
-
-
-
-
-
-
0.2
0.3
0.4
0.6
0.4
0.4
0.55
5
10
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
A
A
0.35
V
CC
V
input leakage current
power-off leakage current
V
CC
= 3.6 V; V
I
= 3.6 V or GND
V
CC
= 0 V; V
I
or V
O
= 0 V to 3.6 V
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 16 May 2014
4 of 14
NXP Semiconductors
74ALVC00-Q100
Quad 2-input NAND gate
Table 6.
Static characteristics
…continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
I
CC
I
CC
C
I
[1]
Conditions
V
CC
= 3.6 V; V
I
= V
CC
or GND;
I
O
= 0 A
per input pin; V
CC
= 3.0 V to 3.6 V;
V
I
= V
CC
0.6 V; I
O
= 0 A
T
amb
=
40 C
to +85
C
Min
Typ
[1]
0.2
5
3.5
Max
20
750
-
-
-
-
Unit
A
A
pF
supply current
additional supply current
input capacitance
All typical values are measured at V
CC
= 3.3 V (unless stated otherwise) and T
amb
= 25
C.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit, see
Figure 7.
Symbol
t
pd
Parameter
propagation delay
Conditions
nA, nB to nY; see
Figure 6
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V
V
CC
= 3.0 V to 3.6 V
C
PD
power dissipation
capacitance
per gate; V
I
= GND to V
CC
; V
CC
= 3.3 V
[3]
[2]
T
amb
=
40 C
to +85
C
Min
1.0
1.0
1.0
1.0
-
Typ
[1]
2.8
2.1
2.6
2.1
28
Max
4.4
2.8
3.2
3.0
-
Unit
ns
ns
ns
ns
pF
[1]
[2]
[3]
Typical values are measured at T
amb
= 25
C
t
pd
is the same as t
PHL
and t
PLH
.
C
PD
is used to determine the dynamic power dissipation (P
D
in
W).
P
D
= C
PD
V
CC2
f
i
N +
(C
L
V
CC2
f
o
) where:
f
i
= input frequency in MHz; f
o
= output frequency in MHz
C
L
= output load capacitance in pF
V
CC
= supply voltage in Volts
N = number of inputs switching
(C
L
V
CC2
f
o
) = sum of the outputs
74ALVC00-Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 16 May 2014
5 of 14
