74ALVC162334A
16-bit registered driver with inverted register enable and 30
Ω
termination resistors (3-state)
Rev. 03 — 13 December 2006
Product data sheet
1. General description
The 74ALVC162334A is a 16-bit universal bus driver. Data flow is controlled by
active LOW output enable (OE), active LOW latch enable (LE), and clock input (CP).
When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held at
LOW or HIGH, the data is latched; on the LOW to HIGH transient of CP, the A data is
stored in the latch/flip-flop.
The 74ALVC162334A is designed with 30
Ω
series resistors in both HIGH or LOW output
stages.
When OE is LOW, the outputs are active. When OE is HIGH, the outputs go to the
high-impedance OFF-state. Operation of the OE input does not affect the state of the
latch/flip-flop.
To ensure the high-impedance state during power-up or power-down, OE should be tied to
V
CC
through a pull-up resistor; the minimum value of the resistor is determined by the
current-sinking capability of the driver.
2. Features
I
I
I
I
I
I
I
I
I
I
Wide supply voltage range of 1.2 V to 3.6 V
Complies with JEDEC standard 8-1A
CMOS low power consumption
Direct interface with TTL levels
Current drive:
±24
mA at 3.0 V
MULTIBYTE flow-through standard pinout architecture
Low inductance multiple V
CC
and GND pins for minimum noise and ground bounce
Output drive capability 50
Ω
transmission lines at 85
°C
Integrated 30
Ω
termination resistors
Input diodes to accommodate strong drivers
NXP Semiconductors
74ALVC162334A
16-bit registered driver (3-state)
3. Quick reference data
Table 1.
Quick reference data
V
CC
= 3.3 V
±
0.3 V; GND = 0 V; t
r
= t
f
≤
2.5 ns; C
L
= 50 pF (see
Figure 11).
Symbol
t
PHL
Parameter
HIGH-to-LOW propagation delay
Conditions
An to Yn;
Figure 5
LE to Yn;
Figure 6
CP to Yn;
Figure 8
t
PLH
LOW-to-HIGH propagation delay
An to Yn;
Figure 5
LE to Yn;
Figure 6
CP to Yn;
Figure 8
f
max
C
i
C
io
C
PD
maximum input clock frequency
input capacitance
input/output capacitance
power dissipation capacitance
per buffer; V
I
= GND to V
CC
transparent mode; output enabled
transparent mode; output disabled
clocked mode; output enabled
clocked mode; output disabled
[1]
[2]
All typical values are at T
amb
= 25
°C.
C
PD
is used to determine the dynamic power dissipation (P
D
) in
µW.
P
D
= C
PD
×
V
CC2
×
f
i
+
Σ
(C
L
×
V
CC2
×
f
o
), where:
f
i
= input frequency in MHz;
C
L
= output load capacitance in pF;
f
o
= output frequency in MHz;
V
CC
= supply voltage in V;
Σ
(C
L
×
V
CC2
×
f
o
) = sum of outputs.
[2]
Min
1.0
1.3
1.4
1.0
1.3
1.4
150
-
-
-
-
-
-
Typ
[1]
2.8
2.8
3.2
2.8
2.8
3.2
240
4.0
8.0
10
3
21
15
Max
4.3
4.4
4.9
4.3
4.4
4.9
-
-
-
-
-
-
-
Unit
ns
ns
ns
ns
ns
ns
MHz
pF
pF
pF
pF
pF
pF
Figure 8
4. Ordering information
Table 2.
Ordering information
Temperature
range
−40 °C
to +85
°C
Package
Name
TSSOP48
Description
plastic thin shrink small outline package;
48 leads; body width 6.1 mm
Version
SOT362-1
Type number
74ALVC162334ADGG
74ALVC162334A_3
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 13 December 2006
2 of 19
NXP Semiconductors
74ALVC162334A
16-bit registered driver (3-state)
5. Functional diagram
1
OE
48
CP
25
LE
EN1
2C3
C3
G2
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
1
1
3D
002aac723
Fig 1. Logic symbol (IEEE/IEC)
OE
CP
LE
A1
D
LE
CP
Y1
to the 15 other channels
002aac724
Fig 2. Logic diagram
V
CC
A1
002aac725
Fig 3. Typical input (data or control)
74ALVC162334A_3
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 13 December 2006
3 of 19
NXP Semiconductors
74ALVC162334A
16-bit registered driver (3-state)
6. Pinning information
6.1 Pinning
OE
Y1
Y2
GND
Y3
Y4
V
CC
Y5
Y6
1
2
3
4
5
6
7
8
9
48 CP
47 A1
46 A2
45 GND
44 A3
43 A4
42 V
CC
41 A5
40 A6
39 GND
38 A7
37 A8
36 A9
35 A10
34 GND
33 A11
32 A12
31 V
CC
30 A13
29 A14
28 GND
27 A15
26 A16
25 LE
002aac722
GND 10
Y7 11
Y8 12
Y9 13
Y10 14
GND 15
Y11 16
Y12 17
V
CC
18
Y13 19
Y14 20
GND 21
Y15 22
Y16 23
n.c. 24
74ALVC162334ADGG
Fig 4. Pin configuration for TSSOP48
6.2 Pin description
Table 3.
Symbol
OE
Y1
Y2
GND
Y3
Y4
V
CC
Y5
Y6
Y7
Y8
74ALVC162334A_3
Pin description
Pin
1
2
3
4, 10, 15, 21,
28, 34, 39, 45
5
6
7, 18, 31, 42
8
9
11
12
Description
output enable input (active LOW)
data output 1
data output 2
ground supply (0 V)
data output 3
data output 4
positive supply voltage
data output 5
data output 6
data output 7
data output 8
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 13 December 2006
4 of 19
NXP Semiconductors
74ALVC162334A
16-bit registered driver (3-state)
Pin description
…continued
Pin
13
14
16
17
19
20
22
23
24
25
26
27
29
30
32
33
35
36
37
38
40
41
43
44
46
47
48
Description
data output 9
data output 10
data output 11
data output 12
data output 13
data output 14
data output 15
data output 16
not connected
latch enable input (active LOW)
data input 16
data input 15
data input 14
data input 13
data input 12
data input 11
data input 10
data input 9
data input 8
data input 7
data input 6
data input 5
data input 4
data input 3
data input 2
data input 1
clock input
Table 3.
Symbol
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
n.c.
LE
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
CP
74ALVC162334A_3
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 13 December 2006
5 of 19
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