74AVC4TD245
4-bit dual supply translating transceiver with configurable
voltage translation; 3-state
Rev. 1 — 3 May 2011
Product data sheet
1. General description
The 74AVC4TD245 is a 4-bit, dual supply transceiver that enables bidirectional level
translation. It features eight 1-bit input-output ports (An and Bn), four direction control
inputs (DIR1, DIR2, DIR3 and DIR4), an output enable input (OE) and dual supply pins
(V
CC(A)
and V
CC(B)
). Both V
CC(A)
and V
CC(B)
can be supplied at any voltage between 0.8 V
and 3.6 V making the device suitable for translating between any of the low voltage nodes
(0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins An, OE and DIRn are referenced to
V
CC(A)
and pins Bn are referenced to V
CC(B)
. A HIGH on DIRn allows transmission from An
to Bn and a LOW on DIRn allows transmission from Bn to An. The output enable input
(OE) can be used to disable the outputs so the buses are effectively isolated.
The device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either V
CC(A)
or V
CC(B)
are at
GND level, both An and Bn are in the high-impedance OFF-state.
2. Features and benefits
Wide supply voltage range:
V
CC(A)
: 0.8 V to 3.6 V
V
CC(B)
: 0.8 V to 3.6 V
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114E Class 3B exceeds 8000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V
Maximum data rates:
380 Mbit/s (≥ 1.8 V to 3.3 V translation)
200 Mbit/s (≥ 1.1 V to 3.3 V translation)
200 Mbit/s (≥ 1.1 V to 2.5 V translation)
200 Mbit/s (≥ 1.1 V to 1.8 V translation)
150 Mbit/s (≥ 1.1 V to 1.5 V translation)
100 Mbit/s (≥ 1.1 V to 1.2 V translation)
NXP Semiconductors
74AVC4TD245
4-bit dual supply translating transceiver; 3-state
Suspend mode
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
I
OFF
circuitry provides partial Power-down mode operation
Multiple package options
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74AVC4TD245PW
−40 °C
to +125
°C
74AVC4TD245BQ
−40 °C
to +125
°C
TSSOP16
Description
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT403-1
SOT763-1
Type number
DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 16 terminals;
body 2.5
×
3.5
×
0.85 mm
XQFN16
plastic, extremely thin quad flat package; no leads;
16 terminals; body 1.80 x 2.60 x 0.50 mm
74AVC4TD245GU
−40 °C
to +125
°C
SOT1161-1
4. Marking
Table 2.
Marking codes
Marking code
C4TD245
4TD245
BD4
Type number
74AVC4TD245PW
74AVC4TD245BQ
74AVC4TD245GU
5. Functional diagram
B1
B2
B3
B4
V
CC(B)
V
CC(A)
OE
A1 DIR1
A2 DIR2
A3 DIR3
A4 DIR4
001aao069
Fig 1.
Logic symbol
74AVC4TD245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 3 May 2011
2 of 26
NXP Semiconductors
74AVC4TD245
4-bit dual supply translating transceiver; 3-state
OE
An
DIRn
Bn
V
CC(A)
V
CC(B)
to next transceiver
001aao070
Fig 2.
Logic diagram (one 1-bit transceiver)
6. Pinning information
6.1 Pinning
74AVC4TD245
V
CC(A)
2
3
4
5
6
7
8
GND
OE
9
GND
(1)
1
terminal 1
index area
16 V
CC(B)
15 DIR2
14 B1
13 B2
12 B3
11 B4
10 DIR3
74AVC4TD245
V
CC(A)
DIR1
A1
A2
A3
A4
DIR4
GND
1
2
3
4
5
6
7
8
001aao072
DIR1
16 V
CC(B)
15 DIR2
14 B1
13 B2
12 B3
11 B4
10 DIR3
9
OE
A1
A2
A3
A4
DIR4
001aao071
Transparent top view
(1) This is not a supply pin, the substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad
however if it is soldered the solder land should remain
floating or be connected to GND.
Fig 3.
Pin configuration SOT403-1 (TSSOP16)
Fig 4.
Pin configuration SOT763-1 (DHVQFN16)
74AVC4TD245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 3 May 2011
3 of 26
NXP Semiconductors
74AVC4TD245
4-bit dual supply translating transceiver; 3-state
74AVC4TD245
16 B1
15 B2
14 B3
terminal 1
index area
13 B4
12 DIR3
11 OE
10 GND
9 DIR4
A4 8
001aao073
DIR2 1
V
CC(B)
2
V
CC(A)
3
DIR1 4
A1 5
A2 6
Transparent top view
Fig 5.
Pin configuration SOT1161-1 (XQFN16)
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
SOT403-1 and
SOT763-1
V
CC(A)
1
SOT1161-1
3
4, 1, 12, 9
5, 6, 7, 8
10
16, 15, 14, 13
11
2
supply voltage A (An, OE and DIRn inputs are
referenced to V
CC(A)
)
direction control input
data input or output
ground (0 V)
data input or output
output enable input (active LOW)
supply voltage B (Bn pins are referenced to V
CC(B)
)
Description
DIR1, DIR2, DIR3, DIR4 2, 15, 10, 7
A1, A2, A3, A4
GND
B1, B2, B3, B4
OE
V
CC(B)
3, 4, 5, 6
8
14, 13, 12, 11
9
16
74AVC4TD245
All information provided in this document is subject to legal disclaimers.
A3 7
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 3 May 2011
4 of 26
NXP Semiconductors
74AVC4TD245
4-bit dual supply translating transceiver; 3-state
7. Functional description
Table 4.
Function table
[1][2]
Input
OE
L
L
L
L
L
L
L
L
H
X
DIR1
L
H
X
X
X
X
X
X
X
X
DIR2
X
X
L
H
X
X
X
X
X
X
DIR3
X
X
X
X
L
H
X
X
X
X
DIR4
X
X
X
X
X
X
L
H
X
X
Input/output
An
A1 = B1
input A1
A2 = B2
input A2
A3 = B3
input A3
A4 = B4
input A4
Z
Z
Bn
input B1
B1 = A1
input B2
B2 = A2
input B3
B3 = A3
input B4
B4 = A4
Z
Z
Supply voltage
V
CC(A)
, V
CC(B)
0.8 V to 3.6 V
0.8 V to 3.6 V
0.8 V to 3.6 V
0.8 V to 3.6 V
0.8 V to 3.6 V
0.8 V to 3.6 V
0.8 V to 3.6 V
0.8 V to 3.6 V
0.8 V to 3.6 V
GND
[3]
[1]
[2]
[3]
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
The An, DIRn and OE input circuit is referenced to V
CC(A)
; The Bn input circuit is referenced to V
CC(B)
.
If at least one of V
CC(A)
or V
CC(B)
is at GND level, the device goes into suspend mode.
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC(A)
V
CC(B)
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
Parameter
supply voltage A
supply voltage B
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
V
O
< 0 V
Active mode
Suspend or 3-state mode
V
O
= 0 V to V
CCO
I
CC(A)
or I
CC(B)
[1][2][3]
[1]
[2]
Conditions
Min
−0.5
−0.5
Max
+4.6
+4.6
-
+4.6
-
V
CCO
+ 0.5
+4.6
±50
100
-
+150
Unit
V
V
mA
V
mA
V
V
mA
mA
mA
°C
V
I
< 0 V
[1]
−50
−0.5
−50
−0.5
−0.5
-
-
−100
−65
74AVC4TD245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 3 May 2011
5 of 26
DSP 与 ARM 处理器
