74AVCH20T245
Rev. 6 — 14 January 2019
20-bit dual supply translating transceiver with configurable
voltage translation; 3-state
Product data sheet
1. General description
The 74AVCH20T245 is a 20-bit, dual supply transceiver that enables bi-directional voltage level
translation. The device can be used as two 10-bit transceivers or as a single 20-bit transceiver.
It features four 10-bit input-output ports (1An, 1Bn and 2An, 2Bn), two output enable inputs
(nOE), two direction inputs (nDIR) and dual supplies (V
CC(A)
and V
CC(B)
). V
CC(A)
and V
CC(B)
can
be independently supplied at any voltage between 0.8 V and 3.6 V making the device suitable for
bi-directional voltage level translation between any of the low voltage nodes: 0.8 V, 1.2 V, 1.5 V,
1.8 V, 2.5 V and 3.3 V. The 1An and 2An ports, nOE and nDIR are referenced to V
CC(A)
, the 1Bn
and 2Bn ports are referenced to V
CC(B)
. A HIGH on a 1DIR allows transmission from 1An to 1Bn
and a LOW on 1DIR allows transmission from 1Bn to 1An. A HIGH on nOE causes the outputs to
assume a HIGH impedance OFF-state.
The device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry
disables the output, preventing any damaging backflow current through the device when it is
powered down. In suspend mode when either V
CC(A)
or V
CC(B)
are at GND level, all output ports will
assume a high impedance OFF-state. The bus hold circuitry on the powered-up side always stays
active.
The 74AVCH20T245 has active bus hold circuitry which is provided to hold unused or floating
data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down
resistors.
2. Features and benefits
•
Wide supply voltage range:
•
V
CC(A)
: 0.8 V to 3.6 V
•
V
CC(B)
: 0.8 V to 3.6 V
Complies with JEDEC standards:
•
JESD8-12 (0.8 V to 1.3 V)
•
JESD8-11 (0.9 V to 1.65 V)
•
JESD8-7 (1.2 V to 1.95 V)
•
JESD8-5 (1.8 V to 2.7 V)
•
JESD8-B (2.7 V to 3.6 V)
ESD protection:
•
HBM JESD22-A114E Class 3B exceeds 8000 V
•
MM JESD22-A115-A exceeds 200 V
•
CDM JESD22-C101C exceeds 1000 V
•
•
Nexperia
74AVCH20T245
20-bit dual supply translating transceiver with configurable voltage translation; 3-state
•
Maximum data rates:
•
380 Mbit/s (≥ 1.8 V to 3.3 V translation)
•
260 Mbit/s (≥ 1.1 V to 3.3 V translation)
•
260 Mbit/s (≥ 1.1 V to 2.5 V translation)
•
210 Mbit/s (≥ 1.1 V to 1.8 V translation)
•
120 Mbit/s (≥ 1.1 V to 1.5 V translation)
•
100 Mbit/s (≥ 1.1 V to 1.2 V translation)
Suspend mode
Bus hold on data inputs
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
I
OFF
circuitry provides partial Power-down mode operation
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C
•
•
•
•
•
•
•
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74AVCH20T245DGG
-40 °C to +125 °C
TSSOP56
Description
plastic thin shrink small outline package;
56 leads; body width 6.1 mm
Version
SOT364-1
4. Functional diagram
1DIR
1OE
1A1
1B1
V
CC(A)
to other nine channels
V
CC(B)
V
CC(A)
to other nine channels
V
CC(B)
2A1
2B1
2DIR
2OE
001aal240
Fig. 1.
Logic diagram
74AVCH20T245
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©
Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 6 — 14 January 2019
2 / 23
Nexperia
74AVCH20T245
20-bit dual supply translating transceiver with configurable voltage translation; 3-state
2
1B1
V
CC(A)
V
CC(B)
3
1B2
5
1B3
6
1B4
8
1B5
9
1B6
10
1B7
12
1B8
13
1B9
14
1B10
56
1OE
1
1DIR
1A1
55
15
2B1
V
CC(A)
V
CC(B)
1A2
54
16
2B2
1A3
52
17
2B3
1A4
51
19
2B4
1A5
49
20
2B5
1A6
48
21
2B6
1A7
47
23
2B7
1A8
45
24
2B8
1A9
44
26
2B9
1A10
43
27
2B10
29
2OE
28
2DIR
2A1
42
2A2
41
2A3
40
2A4
38
2A5
37
2A6
36
2A7
34
2A8
33
2A9
31
2A10
30
001aal239
Fig. 2.
Logic symbol
74AVCH20T245
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©
Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 6 — 14 January 2019
3 / 23
Nexperia
74AVCH20T245
20-bit dual supply translating transceiver with configurable voltage translation; 3-state
5. Pinning information
5.1. Pinning
74AVCH20T245
1DIR
1B1
1B2
GND
1B3
1B4
V
CC(B)
1B5
1B6
1
2
3
4
5
6
7
8
9
56 1OE
55 1A1
54 1A2
53 GND
52 1A3
51 1A4
50 V
CC(A)
49 1A5
48 1A6
47 1A7
46 GND
45 1A8
44 1A9
43 1A10
42 2A1
41 2A2
40 2A3
39 GND
38 2A4
37 2A5
36 2A6
35 V
CC(A)
34 2A7
33 2A8
32 GND
31 2A9
30 2A10
29 2OE
001aal242
1B7 10
GND 11
1B8 12
1B9 13
1B10 14
2B1 15
2B2 16
2B3 17
GND 18
2B4 19
2B5 20
2B6 21
V
CC(B)
22
2B7 23
2B8 24
GND 25
2B9 26
2B10 27
2DIR 28
Fig. 3.
Pin configuration SOT364-1 (TSSOP56)
74AVCH20T245
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 6 — 14 January 2019
4 / 23
Nexperia
74AVCH20T245
20-bit dual supply translating transceiver with configurable voltage translation; 3-state
5.2. Pin description
Table 2. Pin description
Symbol
Pin
1DIR, 2DIR
1, 28
1B1 to 1B10 2, 3, 5, 6, 8, 9, 10, 12, 13, 14
2B1 to 2B10 15, 16, 17, 19, 20, 21, 23, 24,26, 27
GND[1]
V
CC(B)
1OE, 2OE
4, 11, 18, 25, 32, 39, 46, 53
7, 22
56, 29
Description
direction control
data input or output
data input or output
ground (0 V)
supply voltage B (nBn inputs are referenced to V
CC(B)
)
output enable input (active LOW)
data input or output
data input or output
supply voltage A (nAn, nOE and nDIR inputs are referenced to V
CC(A)
)
1A1 to 1A10 55, 54, 52, 51, 49, 48, 47, 45,44, 43
2A1 to 2A10 42, 41, 40, 38, 37, 36, 34, 33,31, 30
V
CC(A)
[1]
35, 50
All GND pins must be connected to ground (0 V).
6. Functional description
Table 3. Function table
[1]
Supply voltage
V
CC(A)
, V
CC(B)
0.8 V to 3.6 V
0.8 V to 3.6 V
0.8 V to 3.6 V
GND
[2]
[1]
[2]
[3]
Input
nOE
[3]
L
L
H
X
nDIR
[3]
L
H
X
X
Input/output
[2]
nAn
[3]
nAn = nBn
input
Z
Z
nBn
[3]
input
nBn = nAn
Z
Z
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
If at least one of V
CC(A)
or V
CC(B)
is at GND level, the device goes into suspend mode.
The nAn, nDIR and nOE input circuit is referenced to V
CC(A)
; The nBn input circuit is referenced to V
CC(B)
.
74AVCH20T245
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 6 — 14 January 2019
5 / 23
嵌入式系统
