54F 74F192 Up Down Decade Counter with Separate Up Down Clocks
November 1994
54F 74F192
Up Down Decade Counter
with Separate Up Down Clocks
General Description
The ’F192 is an up down BCD decade (8421) counter Sep-
arate Count Up and Count Down Clocks are used and in
either counting mode the circuits operate synchronously
The outputs change state synchronously with the LOW-to-
HIGH transitions on the clock inputs
Separate Terminal Count Up and Terminal Count Down out-
puts are used as the clocks for a subsequent stage without
extra logic thus simplifying multistage counter designs Indi-
vidual preset inputs allow the circuit to be used as a pro-
grammable counter Both the Parallel Load (PL) and the
Master Reset (MR) inputs asynchronously override the
clocks
Features
Y
Guaranteed 4000V minimum ESD protection
Commercial
74F192PC
Military
Package
Number
N16E
Package Description
16-Lead (0 300 Wide) Molded Dual-In-Line
16-Lead Ceramic Dual-In-Line
16-Lead (0 150 Wide) Molded Small Outline JEDEC
16-Lead (0 300 Wide) Molded Small Outline EIAJ
16-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
54F192DM (Note 2)
74F192SC (Note 1)
74F192SJ (Note 1)
54F192FM (Note 2)
54F192LM (Note 2)
J16A
M16A
M16D
W16A
E20A
Note 1
Devices also available in 13 reel Use suffix
e
SCX and SJX
Note 2
Military grade device with environmental and burn-in processing Use suffix
e
DMQB FMQB and LMQB
Logic Symbols
Connection Diagrams
Pin Assignment for
DIP SOIC and Flatpak
Pin Assignment
for LCC
TL F 9496–3
IEEE IEC
TL F 9496 – 1
TL F 9496 – 2
TL F 9496–6
TRI-STATE is a registered trademark of National Semiconductor Corporation
C
1995 National Semiconductor Corporation
TL F 9496
RRD-B30M75 Printed in U S A
Unit Loading Fan Out
54F 74F
Pin Names
Description
UL
Input I
IH
I
IL
HIGH LOW Output I
OH
I
OL
10 30
10 30
10 10
10 10
10 10
50 33 3
50 33 3
50 33 3
20
mA
b
1 8 mA
20
mA
b
1 8 mA
20
mA
b
0 6 mA
20
mA
b
0 6 mA
20
mA
b
0 6 mA
b
1 mA 20 mA
b
1 mA 20 mA
b
1 mA 20 mA
CP
U
CP
D
MR
PL
P
0
– P
3
Q
0
– Q
3
TC
D
TC
U
Count Up Clock Input (Active Rising Edge)
Count Down Clock Input (Active Rising Edge)
Asynchronous Master Reset Input (Active HIGH)
Asynchronous Parallel Load Input (Active LOW)
Parallel Data Inputs
Flip-Flop Outputs
Terminal Count Down (Borrow) Output (Active LOW)
Terminal Count Up (Carry) Output (Active LOW)
Functional Description
The ’F192 is an asynchronously presettable decade coun-
ter It contains four edge-triggered flip-flops with internal
gating and steering logic to provide master reset individual
preset count up and count down operations
A LOW-to-HIGH transition on the CP input to each flip-flop
causes the output to change state Synchronous switching
as opposed to ripple counting is achieved by driving the
steering gates of all stages from a common Count Up line
and a common Count Down line thereby causing all state
changes to be initiated simultaneously A LOW-to-HIGH
transition on the Count Up input will advance the count by
one a similar transition on the Count Down input will de-
crease the count by one While counting with one clock in-
put the other should be held HIGH as indicated in the
Function Table Otherwise the circuit will either count by
twos or not at all depending on the state of the first flip-flop
which cannot toggle as long as either clock input is LOW
The Terminal Count Up (TC
U
) and Terminal Count Down
(TC
D
) outputs are normally HIGH When the circuit has
reached the maximum count state 9 the next HIGH-to-LOW
transition of the Count Up Clock will cause TC
U
to go LOW
TC
U
will stay LOW until CP
U
goes HIGH again thus effec-
tively repeating the Count Up Clock but delayed by two
gate delays Similarly the TC
D
output will go LOW when the
circuit is in the zero state and the Count Down Clock goes
LOW Since the TC outputs repeat the clock waveforms
they can be used as the clock input signals to the next
higher order circuit in a multistage counter
TC
U
e
Q
0
Q
3
CP
U
TC
D
e
Q
0
Q
1
Q
2
Q
3
CP
D
The ’F192 has an asynchronous parallel load capability per-
mitting the counter to be preset When the Parallel Load
(PL) and the Master Reset (MR) inputs are LOW informa-
tion present on the Parallel Data input (P
0
– P
3
) is loaded
into the counter and appears on the outputs regardless of
the conditions of the clock inputs A HIGH signal on the
Master Reset input will disable the preset gates override
both clock inputs and latch each Q output in the LOW state
If one of the clock inputs is LOW during and after a reset or
TL F 9496 – 4
load operation the next LOW-to-HIGH transition of that
clock will be interpreted as a legitimate signal and will be
counted
Function Table
MR
H
L
L
L
L
PL
X
L
H
H
H
CP
U
X
X
H
L
H
CP
D
X
X
H
H
L
Mode
Reset (Asyn )
Preset (Asyn )
No Change
Count Up
Count Down
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
L
e
LOW-to-HIGH Clock Transition
State Diagram
2
Logic Diagram
TL F 9496 – 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
3
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
b
65 C to
a
150 C
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
Plastic
V
CC
Pin Potential to
Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with V
CC
e
0V)
Standard Output
TRI-STATE Output
Current Applied to Output
in LOW State (Max)
b
55 C to
a
125 C
b
55 C to
a
175 C
b
55 C to
a
150 C
b
0 5V to
a
7 0V
b
0 5V to
a
7 0V
b
30 mA to
a
5 0 mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
Commercial
Supply Voltage
Military
Commercial
b
55 C to
a
125 C
0 C to
a
70 C
a
4 5V to
a
5 5V
a
4 5V to
a
5 5V
b
0 5V to V
CC
b
0 5V to
a
5 5V
twice the rated I
OL
(mA)
Note 1
Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired Functional operation under
these conditions is not implied
Note 2
Either voltage limit or current limit is sufficient to protect inputs
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
Parameter
Min
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Current
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
Input LOW Current
Output Short-Circuit Current
Power Supply Current
b
60
54F 74F
Typ
Max
Units
V
08
b
1 2
V
CC
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
20
V
V
V
Min
Min
I
IN
e b
18 mA
I
OH
e b
1 mA
I
OH
e b
1 mA
I
OH
e b
1 mA
I
OL
e
20 mA
I
OL
e
20 mA
V
IN
e
2 7V
V
IN
e
7 0V
V
OUT
e
V
CC
I
ID
e
1 9
mA
All Other Pins Grounded
V
IOD
e
150 mV
All Other Pins Grounded
V
IN
e
0 5V Except CP
u
CP
D
V
IN
e
0 5V CP
u
CP
D
V
OUT
e
0V
V
O
e
LOW
54F 10% V
CC
74F 10% V
CC
74F 5% V
CC
54F 10% V
CC
74F 10% V
CC
54F
74F
54F
74F
54F
74F
74F
74F
25
25
27
05
05
20 0
50
100
70
250
50
4 75
3 75
b
0 6
b
1 8
b
150
V
OL
I
IH
I
BVI
I
CEX
V
ID
I
OD
I
IL
I
OS
I
CCL
V
mA
mA
mA
V
mA
mA
mA
mA
Min
Max
Max
Max
00
00
Max
Max
Max
38
55
4
AC Electrical Characteristics
74F
Symbol
Parameter
Min
f
max
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
Maximum Clock Frequency
Propagation Delay CP
U
or
CP
D
to TC
U
or TC
D
Propagation Delay
CP
U
or CP
D
to Q
n
Propagation Delay
P
n
to Q
n
Propagation Delay
PL to Q
n
Propagation Delay
MR to Q
n
Propagation Delay
MR to TC
U
Propagation Delay
MR to TC
D
Propagation Delay
PL to TC
U
or TC
D
Propagation Delay
P
n
to TC
U
or TC
D
100
40
35
40
55
30
60
50
55
65
60
70
70
70
70
65
T
A
e a
25 C
V
CC
e a
5 0V
C
L
e
50 pF
Typ
125
70
60
65
95
45
11 0
85
10 0
11 0
10 5
11 5
12 0
11 5
11 5
11 0
90
80
85
12 5
70
14 5
11 0
13 0
14 5
13 5
14 5
15 5
14 5
14 5
14 0
Max
54F
T
A
V
CC
e
Mil
C
L
e
50 pF
Min
75
40
35
40
55
30
60
50
55
65
60
70
70
70
70
65
10 5
95
10 0
14 0
85
16 5
13 5
15 0
16 0
15 0
16 0
18 5
17 5
16 5
16 5
Max
74F
T
A
V
CC
e
Com
C
L
e
50 pF
Min
90
40
35
40
55
30
60
50
55
65
60
70
70
70
70
65
10 0
90
95
13 5
80
15 5
12 0
14 0
15 5
14 5
15 5
16 5
15 5
15 5
15 0
ns
ns
ns
Max
MHz
ns
ns
ns
ns
Units
AC Operating Requirements
74F
Symbol
Parameter
T
A
e a
25 C
V
CC
e a
5 0V
Min
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
w
(L)
t
w
(L)
t
w
(L)
Setup Time HIGH or LOW
P
n
to PL
Hold Time HIGH or LOW
P
n
to PL
PL Pulse Width LOW
CP
U
or CP
D
Pulse Width LOW
CP
U
or CP
D
Pulse Width LOW
(Change of Direction)
MR Pulse Width HIGH
Recovery Time
PL to CP
U
or CP
D
Recovery Time
MR to CP
U
or CP
D
45
45
20
20
60
50
Max
54F
T
A
V
CC
e
Mil
Min
60
60
20
20
75
70
Max
74F
T
A
V
CC
e
Com
Min
50
50
20
20
60
50
ns
ns
Max
Units
ns
10 0
60
60
40
12 0
60
80
45
10 0
60
60
40
ns
ns
ns
ns
t
w
(H)
t
rec
t
rec
5
