INTEGRATED CIRCUITS
74F50109
Synchronizing dual J-K positive
edge-triggered flip-flop with metastable
immune characteristics
Product specification
IC15 Data Handbook
1990 Sep 14
Philips
Semiconductors
Philips Semiconductors
Product specification
Synchronizing dual J–K positive edge-triggered
flip-flop with metastable immune characteristics
74F50109
FEATURE
•
Metastable immune characteristics
•
Output skew guaranteed less than 1.5ns
•
High source current (I
OH
= 15mA) ideal for clock driver
applications
PIN CONFIGURATION
RD0
1
16 V
CC
15 RD1
14
J1
J0 2
K0 3
CP0 4
SD0 5
Q0 6
Q0 7
GND 8
•
Pinout compatible with 74F109
•
See 74F5074 for synchronizing dual D-type flip-flop
•
See 74F50728 for synchronizing cascaded D-type flip-flop
•
See 74F50729 for synchronizing dual D-type flip-flop with
edge-triggered set and reset
TYPE
74F50109
TYPICAL f
max
150MHz
TYPICAL SUPPLY
CURRENT( TOTAL)
22mA
13 K1
12 CP1
11 SD1
10 Q1
9
Q1
SF00598
LOGIC SYMBOL
2 14
3 13
ORDERING INFORMATION
ORDER CODE
COMMERCIAL RANGE
DESCRIPTION
T
amb
= 0
°
C to +70
°
C
16–pin plastic DIP
16–pin plastic SO
N74F50109N
N74F50109D
SOT38-4
SOT109-1
V
CC
= 5V
±
10%,
PKG DWG #
4
5
1
12
11
15
CP0 J0
SD0
RD0
CP1
SD1
RD1
J1
K0 K1
Q0 Q0 Q1 Q1
INPUT AND OUTPUT LOADING
AND FAN OUT TABLE
PINS
J0, J1
K0, K1
CP0, CP1
SD0, SD1
RD0, RD1
DESCRIPTION
J inputs
K inputs
Clock inputs
(active rising edge)
Set inputs
(active low)
Reset inputs
(active low)
74F (U.L.)
HIGH/
LOW
1.0/0.417
1.0/0.417
1.0/0.033
1.0/0.033
1.0/0.033
LOAD
VALUE
HIGH/LOW
20µA/250µA
20µA/250µA
6
V
CC
= Pin 16
GND = Pin 8
7
10
9
SF00599
IEC/IEEE SYMBOL
2
1J
C1
1K
R
S
2J
C2
2K
R
S
9
10
7
20µA/20µA
20µA/20µA
20µA/20µA
4
3
1
5
14
6
Q0, Q1, Q0, Q1 Data outputs
750/33
15mA/20mA
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the high
state and 0.6mA in the low state.
12
13
15
11
SF00600
September 14, 1990
2
853-1388 00422
Philips Semiconductors
Product specification
Synchronizing dual J–K positive edge-triggered
flip-flop with metastable immune characteristics
74F50109
LOGIC DIAGRAM
7, 9
6, 10
Q
Q
device–under–test can be often be driven into a metastable state. If
the Q output is then used to trigger a digital scope set to infinite
persistence the Q output will build a waveform.0 An experiment was
run by continuously operating the devices in the region where
metastability will occur.
When the device–under–test is a 74F74 (which was not designed
with metastable immune characteristics) the waveform will appear
as in Fig. 2.
K
3, 13
J
CP
SD
RD
2, 14
4, 12
5, 11
1, 15
Fig. 2 shows clearly that the Q output can vary in time with respect
to the Q trigger point. This also implies that the Q or Q output
waveshapes may be distorted. This can be verified on an analog
scope with a charge plate CRT. Perhaps of even greater interest are
the dots running along the 3.5V volt line in the upper right hand
quadrant. These show that the Q output did not change state even
though the Q output glitched to at least 1.5 volts, the trigger point of
the scope.
When the device–under–test is a metastable immune part, such as
the 74F5074, the waveform will appear as in Fig. 3. The 74F5074 Q
output will appear as in Fig. 3. The 74F5074 Q output will not vary
with respect to the Q trigger point even when the a part is driven into
a metastable state. Any tendency towards internal metastability is
resolved by Philips Semiconductors patented circuitry. If a
metastable event occurs within the flop the only outward
manifestation of the event will be an increased clock–to–Q/Q
propagation delay. This propagation delay is, of course, a function of
the metastability characteristics of the part defined by
τ
and T
0.
The metastability characteristics of the 74F5074 and related part
types represent state–of–the–art TTL technology.
After determining the T
0
and t of the flop, calculating the mean time
between failures (MTBF) is simple. Suppose a designer wants to
use the 74F50729 for synchronizing asynchronous data that is
arriving at 10MHz (as measured by a frequency counter), has a
clock frequency of 50MHz, and has decided that he would like to
sample the output of the 74F50109 10 nanoseconds after the clock
edge. He simply plugs his number into the equation below:
MTBF = e
(t’/t)
/ T
o
f
C
f
I
In this formula, f
C
is the frequency of the clock, f
I
is the average
input event frequency, and t’ is the time after the clock pulse that the
output is sampled (t’ < h, h being the normal propagation delay). In
this situation the f
I
will be twice the data frequency of 20 MHz
because input events consist of both of low and high transitions.
Multiplying f
I
by f
C
gives an answer of 10
15
Hz
2
. From Fig. 4 it is
clear that the MTBF is greater than 10
10
seconds. Using the above
formula MTBF is 1.51 X 10
10
seconds or about 480 years.
V
CC
= Pin 16
GND = Pin 8
SF00601
DESCRIPTION
The 74F50109 is a dual positive edge-triggered JK-type flip-flop
featuring individual J, K, clock, set, and reset inputs; also true and
complementary outputs.
Set (SD) and reset (RD) are asynchronous active low inputs and
operate independently of the clock (CP) input.
The J and K are edge–triggered inputs which control the state
changes of the flip–flops as described in the function table.
The J and K inputs must be stable just one setup time prior to the
low–to–high transition of the clock for guaranteed propagation
delays. The JK design allows operation as a D flip–flop by tying J
and K inputs together.
The 74F50109 is designed so that the outputs can never display a
metastable state due to setup and hold time violations. If setup time
and hold time are violated the propagation delays may be extended
beyond the specifications but the outputs will not glitch or display a
metastable state. Typical metastability parameters for the 74F50109
are:
τ ≅ 135ps
and
τ ≅
9.8 X 10
6
sec where
τ
represents a function
of the rate at which a latch in a metastable state resolves that
condition and T
0
represents a function of the measurement of the
propensity of a latch to enter a metastable state.
METASTABLE IMMUNE CHARACTERISTICS
Philips Semiconductors uses the term ’metastable immune’ to
describe characteristics of some of the products in its FAST family.
Specifically the 74F50XXX family presently consist of 4 products
which displays metastable immune characteristics. This term means
that the outputs will not glitch or display an output anomaly under
any circumstances including setup and hold time violations.
This claim is easily verified on the 74F5074. By running two
independent signal generators (see Fig. 1) at nearly the same
frequency (in this case 10MHz clock and 10.02 MHz data) the
SIGNAL GENERATOR
D
Q
TRIGGER
DIGITAL
SCOPE
SIGNAL GENERATOR
CP
Q
INPUT
SF00586
Figure 1. Test setup
September 14, 1990
3
Philips Semiconductors
Product specification
Synchronizing dual J–K positive edge-triggered
flip-flop with metastable immune characteristics
74F50109
COMPARISON OF METASTABLE IMMUNE AND NON–IMMUNE CHARACTERISTICS
4
3
2
1
0
Time base = 2.00ns/div Trigger level = 1.5 Volts Trigger slope = positive
SF00602
Figure 2. 74F74 Q output triggered by Q output, Setup and Hold times violated
3
2
1
0
Time base = 2.00ns/div Trigger level = 1.5 Volts Trigger slope = positive
SF00588
Figure 3. 74F74 Q output triggered by Q output, Setup and Hold times violated
September 14, 1990
4
Philips Semiconductors
Product specification
Synchronizing dual J–K positive edge-triggered
flip-flop with metastable immune characteristics
74F50109
MEAN TIME BETWEEN FAILURES (MTBF) VERSUS t’
10
6
10
8
10
10
10
12
10
14
10
12
10
11
10,000 years
10
10
100 years
MTBF in seconds
10
8
one year
10
7
10
6
one week
7
8
9
10
SF00589
10
15
= f
C
f
I
10
9
t’ in nanoseconds
NOTE:
V
CC
= 5V, T
amb
= 25°C,
τ
=135ps, To = 9.8 X 10
8
sec
Figure 4.
TYPICAL VALUES FOR
τ
AND T
0
AT VARIOUS V
CC
S AND TEMPERATURES
T
amb
= 0
°
C
T
amb
= 25
°
C
V
CC
5.5V
5.0V
4.5V
τ
125ps
115ps
115ps
T
0
1.0 X 10
9
sec
1.3 X 10
10
sec
3.4 X 10
13
sec
τ
138ps
135ps
132ps
T
0
5.4 X 10
6
sec
9.8 X 10
6
sec
5.1 X 10
8
sec
τ
160ps
167ps
175ps
T
amb
= 70
°
C
T
0
1.7 X 10
5
sec
3.9 X 10
4
sec
7.3 X 10
4
sec
FUNCTION TABLE
INPUTS
SD
L
H
L
H
H
H
H
H
RD
H
L
L
H
H
H
H
H
CP
X
X
X
↑
↑
↑
↑
↑
J
X
X
X
X
h
h
l
l
K
X
X
X
X
l
h
l
h
OUTPUTS
Q
H
L
H
q
q
H
L
q
Q
L
H
H
q
q
L
H
q
OPERATING
MODE
Asynchronous set
Asynchronous reset
Undetermined*
Hold
Toggle
Load ”1” (set)
Load ”0” (reset)
Hold ’no change”
NOTES:
H = High–voltage level
h = High–voltage level one setup time prior to
low–to–high clock transition
L = Low–voltage level
l = Low–voltage level one setup time prior to
low–to–high clock
transition
q = Lower case indicate the state of the referenced
output prior to the low–to–high clock transition
X = Don’t care
↑
= Low–to–high clock transition
↑
= Not low–to–high clock transition
* = Both outputs will be high if both SD and RD go low
simultaneously
September 14, 1990
5
