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74F540_00

Octal inverter buffer 3- State

厂商名称:Fairchild

厂商官网:http://www.fairchildsemi.com/

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74F540 • 74F541 Octal Buffer/Line Driver with 3-STATE Outputs
April 1988
Revised October 2000
74F540 • 74F541
Octal Buffer/Line Driver with 3-STATE Outputs
General Description
The 74F540 and 74F541 are similar in function to the
74F240 and 74F244 respectively, except that the inputs
and outputs are on opposite sides of the package (see
Connection Diagrams). This pinout arrangement makes
these devices especially useful as output ports for micro-
processors, allowing ease of layout and greater PC board
density.
Features
s
3-STATE outputs drive bus lines
s
Inputs and outputs opposite side of package, allowing
easier interface to microprocessors
Ordering Code:
Order Number
74F540SC
74F540SJ
74F540PC
74F541SC
74F541SJ
74F541PC
Package Number
M20B
M20D
N20A
M20B
M20D
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
74F540
Connection Diagrams
74F540
IEEE/IEC
74F541
74F541
© 2000 Fairchild Semiconductor Corporation
DS009553
www.fairchildsemi.com
74F540 • 74F541
Unit Loading/Fan Out
U.L.
Pin Names
OE
1
, OE
2
I
n
O
n
, O
n
Description
HIGH/LOW
3-STATE Output Enable Input (Active LOW)
Inputs
Outputs
1.0/1.0
1.0/1.0
Input I
IH
/I
IL
Output I
OH
/I
OL
20
µ
A/
0.6 mA
20
µ
A/
0.6 mA
600/106.6 (80)
12 mA/64 mA (48 mA)
Truth Table
Inputs
OE
1
L
H
X
L
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
Outputs
I
H
X
X
L
74F540
L
Z
Z
H
74F541
H
Z
Z
L
OE
2
L
X
H
L
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2
74F540 • 74F541
Absolute Maximum Ratings
(Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
3-STATE Output
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
65
°
C to
+
150
°
C
55
°
C to
+
125
°
C
55
°
C to
+
150
°
C
0.5V to
+
7.0V
0.5V to
+
7.0V
30 mA to
+
5.0 mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0
°
C to
+
70
°
C
+
4.5V to
+
5.5V
0.5V to V
CC
0.5V to
+
5.5V
Note 1:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
V
OL
I
IH
I
BVI
I
CEX
V
ID
I
OD
I
IL
I
OZH
I
OZL
I
OS
I
ZZ
I
CCH
I
CCL
I
CCZ
I
CCH
I
CCL
I
CCZ
Output LOW Voltage
Input HIGH
Current
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current (74F540)
Power Supply Current (74F540)
Power Supply Current (74F540)
Power Supply Current (74F541)
Power Supply Current (74F541)
Power Supply Current (74F541)
11
53
31
26
55
31
−100
4.75
3.75
−0.6
50
−50
−225
500
20
75
45
35
75
55
10% V
CC
10% V
CC
5% V
CC
10% V
CC
2.4
2.0
2.7
0.55
5.0
7.0
50
V
µA
µA
µA
V
µA
mA
µA
µA
mA
µA
mA
mA
mA
mA
mA
mA
Min
Max
Max
Max
0.0
0.0
Max
Max
Max
Max
0.0V
Max
Max
Max
Max
Max
Max
V
Min
Min
2.0
0.8
−1.2
Typ
Max
Units
V
V
V
Min
V
CC
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
I
IN
= −18
mA
I
OH
= −3
mA
I
OH
= −15
mA
I
OH
= −3
mA
I
OL
=
64 mA
V
IN
=
2.7V
V
IN
=
7.0V
V
OUT
=
V
CC
I
ID
=
1.9
µA
All Other Pins Grounded
V
IOD
=
150 mV
All Other Pins Grounded
V
IN
=
0.5V
V
OUT
=
2.7V
V
OUT
=
0.5V
V
OUT
=
0V
V
OUT
=
5.25V
V
O
=
HIGH
V
O
=
LOW
V
O
=
HIGH Z
V
O
=
HIGH
V
O
=
LOW
V
O
=
HIGH Z
3
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74F540 • 74F541
AC Electrical Characteristics
T
A
= +25°C
Symbol
Parameter
Min
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Output Disable Time (74F541)
Propagation Delay
Data to Output (74F541)
Output Enable Time (74F541)
Output Disable Time (74F540)
Propagation Delay
Data to Output (74F540)
Output Enable Time (74F540)
1.5
1.0
2.5
3.5
1.5
1.0
1.5
1.5
3.0
3.5
1.5
1.5
V
CC
= +5.0V
C
L
=
50 pF
Typ
3.0
2.0
4.9
5.8
3.4
2.5
3.3
2.7
5.8
6.1
3.4
2.9
Max
5.0
4.0
8.0
10.0
6.0
5.5
5.5
5.5
8.0
8.5
6.0
5.5
T
A
= −55°C
to
+125°C
V
CC
= +5.0V
C
L
=
50 pF
Min
1.0
1.0
2.5
3.5
1.5
1.0
Max
6.0
4.5
9.0
11.0
7.0
7.5
T
A
=
0°C to
+70°C
V
CC
= +5.0V
C
L
=
50 pF
Min
1.0
1.0
2.5
3.5
1.5
1.0
1.5
1.5
2.5
3.0
1.5
1.5
Max
5.5
4.0
8.5
10.5
6.5
6.0
6.0
6.0
9.5
9.5
6.5
6.0
ns
ns
ns
ns
Units
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4
74F540 • 74F541
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
5
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参数对比
与74F540_00相近的元器件有:74F540SJ、74F541、74F540SC、74F541SJ、74F541SC、74F541PC、74F540PC。描述及对比如下:
型号 74F540_00 74F540SJ 74F541 74F540SC 74F541SJ 74F541SC 74F541PC 74F540PC
描述 Octal inverter buffer 3- State Octal inverter buffer 3- State Octal inverter buffer 3- State Octal inverter buffer 3- State Octal inverter buffer 3- State F/FAST SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20 Octal inverter buffer 3- State Octal inverter buffer 3- State
是否Rohs认证 - 符合 - 符合 符合 符合 符合 符合
厂商名称 - Fairchild - Fairchild Fairchild Fairchild Fairchild Fairchild
零件包装代码 - SOIC - SOIC SOIC SOIC DIP DIP
包装说明 - SOP, SOP20,.3 - SOP, SOP20,.4 SOP, SOP20,.3 0.300 INCH, MS-013, SOIC-20 0.300 INCH, PLASTIC, MS-001, DIP-20 DIP, DIP20,.3
针数 - 20 - 20 20 20 20 20
Reach Compliance Code - compliant - unknow compli unknow unknow unknow
其他特性 - WITH DUAL OUTPUT ENABLE - WITH DUAL OUTPUT ENABLE WITH DUAL OUTPUT ENABLE WITH DUAL OUTPUT ENABLE WITH DUAL OUTPUT ENABLE WITH DUAL OUTPUT ENABLE
控制类型 - ENABLE LOW - ENABLE LOW ENABLE LOW ENABLE LOW ENABLE LOW ENABLE LOW
系列 - F/FAST - F/FAST F/FAST F/FAST F/FAST F/FAST
JESD-30 代码 - R-PDSO-G20 - R-PDSO-G20 R-PDSO-G20 R-PDSO-G20 R-PDIP-T20 R-PDIP-T20
JESD-609代码 - e3 - e3 e3 e3 e3 e3
长度 - 12.6 mm - 12.8 mm 12.6 mm 12.8 mm 26.075 mm 26.075 mm
逻辑集成电路类型 - BUS DRIVER - BUS DRIVER BUS DRIVER BUS DRIVER BUS DRIVER BUS DRIVER
最大I(ol) - 0.064 A - 0.064 A 0.064 A 0.064 A 0.064 A 0.064 A
位数 - 8 - 8 8 8 8 8
功能数量 - 1 - 1 1 1 1 1
端口数量 - 2 - 2 2 2 2 2
端子数量 - 20 - 20 20 20 20 20
最高工作温度 - 70 °C - 70 °C 70 °C 70 °C 70 °C 70 °C
输出特性 - 3-STATE - 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE
输出极性 - INVERTED - INVERTED TRUE TRUE TRUE INVERTED
封装主体材料 - PLASTIC/EPOXY - PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 - SOP - SOP SOP SOP DIP DIP
封装等效代码 - SOP20,.3 - SOP20,.4 SOP20,.3 SOP20,.4 DIP20,.3 DIP20,.3
封装形状 - RECTANGULAR - RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 - SMALL OUTLINE - SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE IN-LINE IN-LINE
峰值回流温度(摄氏度) - 260 - 260 260 260 NOT APPLICABLE NOT APPLICABLE
电源 - 5 V - 5 V 5 V 5 V 5 V 5 V
最大电源电流(ICC) - 75 mA - 75 mA 75 mA 75 mA 75 mA 75 mA
传播延迟(tpd) - 5.5 ns - 5.5 ns 6 ns 6 ns 6 ns 5.5 ns
认证状态 - Not Qualified - Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
座面最大高度 - 2.1 mm - 2.65 mm 2.1 mm 2.65 mm 5.08 mm 5.08 mm
最大供电电压 (Vsup) - 5.5 V - 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V
最小供电电压 (Vsup) - 4.5 V - 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V
标称供电电压 (Vsup) - 5 V - 5 V 5 V 5 V 5 V 5 V
表面贴装 - YES - YES YES YES NO NO
技术 - TTL - TTL TTL TTL TTL TTL
温度等级 - COMMERCIAL - COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
端子面层 - Matte Tin (Sn) - Matte Tin (Sn) Matte Tin (Sn) Matte Tin (Sn) Matte Tin (Sn) Matte Tin (Sn)
端子形式 - GULL WING - GULL WING GULL WING GULL WING THROUGH-HOLE THROUGH-HOLE
端子节距 - 1.27 mm - 1.27 mm 1.27 mm 1.27 mm 2.54 mm 2.54 mm
端子位置 - DUAL - DUAL DUAL DUAL DUAL DUAL
处于峰值回流温度下的最长时间 - NOT SPECIFIED - NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT APPLICABLE NOT APPLICABLE
宽度 - 5.3 mm - 7.5 mm 5.3 mm 7.5 mm 7.62 mm 7.62 mm
Base Number Matches - 1 - 1 1 1 1 1
Prop。Delay @ Nom-Su - - - 5.5 ns 6 ns 6 ns 6 ns 5.5 ns
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