54F 74F573 Octal D-Type Latch with TRI-STATE Outputs
August 1995
54F 74F573
Octal D-Type Latch with TRI-STATE Outputs
General Description
The ’F573 is a high speed octal latch with buffered common
Latch Enable (LE) and buffered common Output Enable
(OE) inputs
This device is functionally identical to the ’F373 but has
different pinouts
Features
Y
Y
Y
Y
Y
Inputs and outputs on opposite sides of package
allowing easy interface with microprocessors
Useful as input or output port for microprocessors
Functionally identical to ’F373
TRI-STATE outputs for bus interfacing
Guaranteed 4000V minimum ESD protection
Commercial
74F573PC
Military
Package
Number
N20A
Package Description
20-Lead (0 300 Wide) Molded Dual-In-Line
20-Lead Ceramic Dual-In-Line
20-Lead (0 300 Wide) Molded Small Outline JEDEC
20-Lead (0 300 Wide) Molded Small Outline EIAJ
20-Lead Cerpak
20-Lead Ceramic Leadless Chip Carrier Type C
54F573DM (Note 2)
74F573SC (Note 1)
74F573SJ (Note 1)
54F573FM (Note 2)
54F573LM (Note 2)
J20A
M20B
M20D
W20A
E20A
Note 1
Devices also available in 13 reel Use suffix
e
SCX and SJX
Note 2
Military grade device with environmental and burn-in processing Use suffix
e
DMQB FMQB and LMQB
Logic Symbols
Connection Diagrams
Pin Assignment for
DIP SOIC and Flatpak
Pin Assignment
for LCC
TL F 9566–1
IEEE IEC
TL F 9566 – 3
TL F 9566 – 2
TL F 9566–4
TRI-STATE is a registered trademark of National Semiconductor Corporation
C
1995 National Semiconductor Corporation
TL F 9566
RRD-B30M115 Printed in U S A
Unit Loading Fan Out
54F 74F
Pin Names
Description
UL
HIGH LOW
10 10
10 10
10 10
150 40(33 3)
Input I
IH
I
IL
Output I
OH
I
OL
20
mA
b
0 6 mA
20
mA
b
0 6 mA
20
mA
b
0 6 mA
b
3 mA 24 mA (20 mA)
D
0
– D
7
LE
OE
O
0
– O
7
Data Inputs
Latch Enable Input (Active HIGH)
TRI-STATE Output Enable Input
(Active LOW)
TRI-STATE Latch Outputs
Functional Description
The ’F573 contains eight D-type latches with 3-state output
buffers When the Latch Enable (LE) input is HIGH data on
the D
n
inputs enters the latches In this condition the latch-
es are transparent i e a latch output will change state each
time its D input changes When LE is LOW the latches store
the information that was present on the D inputs a setup
time preceding the HIGH-to-LOW transition of LE The 3-
state buffers are controlled by the Output Enable (OE) input
When OE is LOW the buffers are in the bi-state mode
When OE is HIGH the buffers are in the high impedance
mode but this does not interfer with entering new data into
the latches
Function Table
Inputs
OE
L
L
L
H
LE
H
H
L
X
D
H
L
X
X
Outputs
O
H
L
O
0
Z
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
O
0
e
Value stored from previous clock cycle
Logic Diagram
TL F 9566 – 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
b
65 C to
a
150 C
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
Plastic
V
CC
Pin Potential to
Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with V
CC
e
0V)
Standard Output
TRI-STATE Output
Current Applied to Output
in LOW State (Max)
ESD Last Passing Voltage (Min)
b
55 C to
a
125 C
b
55 C to
a
175 C
b
55 C to
a
150 C
b
0 5V to
a
7 0V
b
0 5V to
a
7 0V
b
30 mA to
a
5 0 mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
Commercial
Supply Voltage
Military
Commercial
b
55 C to
a
125 C
0 C to
a
70 C
a
4 5V to
a
5 5V
a
4 5V to
a
5 5V
b
0 5V to V
CC
b
0 5V to
a
5 5V
twice the rated I
OL
(mA)
4000V
Note 1
Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired Functional operation under
these conditions is not implied
Note 2
Either voltage limit or current limit is sufficient to protect inputs
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
Parameter
Min
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
54F 10% V
CC
54F 10% V
CC
74F 10% V
CC
74F 10% V
CC
74F 5% V
CC
74F 5% V
CC
54F 10% V
CC
74F 10% V
CC
54F
74F
54F
74F
54F
74F
74F
74F
4 75
3 75
b
0 6
54F 74F
Typ
Max
Units
V
08
b
1 2
V
CC
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
20
V
V
Min
I
IN
e b
18 mA
I
OH
I
OH
I
OH
I
OH
I
OH
I
OH
e
e
e
e
e
e
b
1 mA
b
3 mA
b
1 mA
b
3 mA
b
1 mA
b
3 mA
25
24
25
24
27
27
05
05
20 0
50
100
70
250
50
V
Min
V
OL
I
IH
I
BVI
I
CEX
V
ID
I
OD
I
IL
I
OZH
I
OZL
I
OS
I
ZZ
I
CCL
I
CCZ
Output LOW
Voltage
Input HIGH
Current
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
Input LOW Current
V
mA
mA
mA
V
mA
mA
mA
mA
mA
mA
mA
mA
Min
Max
Max
Max
00
00
Max
Max
Max
Max
0 0V
Max
Max
I
OL
e
20 mA
I
OL
e
24 mA
V
IN
e
2 7V
V
IN
e
7 0V
V
OUT
e
V
CC
I
ID
e
1 9
mA
All Other Pins Grounded
V
IOD
e
150 mV
All Other Pins Grounded
V
IN
e
0 5V
V
OUT
e
2 7V
V
OUT
e
0 5V
V
OUT
e
0V
V
OUT
e
5 25V
V
O
e
LOW
V
O
e
HIGH Z
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current
Power Supply Current
35
35
b
60
50
b
50
b
150
500
55
55
3
AC Electrical Characteristics
74F
Symbol
Parameter
Min
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation Delay
D
n
to O
n
Propagation Delay
LE to O
n
Output Enable Time
Output Disable Time
30
20
50
30
20
20
15
15
T
A
e a
25 C
V
CC
e a
5 0V
C
L
e
50 pF
Typ
53
37
90
52
50
56
45
38
Max
70
60
11 0
70
80
85
55
55
54F
T
A
V
CC
e
Mil
C
L
e
50 pF
Min
30
20
50
30
20
20
15
15
Max
90
70
13 5
75
10 0
10 0
70
55
74F
T
A
V
CC
e
Com
C
L
e
50 pF
Min
30
20
50
30
20
20
15
15
Max
80
65
12 0
70
90
95
65
55
ns
ns
Units
ns
AC Operating Requirements
74F
Symbol
Parameter
T
A
e a
25 C
V
CC
e a
5 0V
Min
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
w
(H)
Setup Time HIGH or LOW
D
n
to LE
Hold Time HIGH or LOW
D
n
to LE
LE Pulse Width HIGH
20
20
30
35
40
Max
54F
T
A
V
CC
e
Mil
Min
20
20
30
40
40
Max
74F
T
A
V
CC
e
Com
Min
20
20
30
35
40
ns
Max
Units
ns
4
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows
74F
Temperature Range Family
74F
e
Commercial
54F
e
Military
Device Type
Package Code
P
e
Plastic DIP
D
e
Ceramic DIP
F
e
Flatpak
L
e
Leadless Chip Carrier (LCC)
S
e
Small Outline SOIC JEDEC
SJ
e
Small Outline SOIC EIAJ
573
S
C
X
Special Variations
QB
e
Military grade device with
environmental and burn-in
processing
X
e
Devices shipped in 13 reels
Temperature Range
C
e
Commercial (0 C to
a
70 C)
M
e
Military (
b
55 C to
a
125 C)
Physical Dimensions
inches (millimeters)
20-Lead Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
5
模拟电子
