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74FCT2240TP

PDIP-20, Tube

器件类别:逻辑    逻辑   

厂商名称:IDT (Integrated Device Technology)

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器件参数
参数名称
属性值
Brand Name
Integrated Device Technology
是否无铅
含铅
是否Rohs认证
不符合
Objectid
1382316822
零件包装代码
PDIP
包装说明
DIP, DIP20,.3
针数
20
制造商包装代码
PD20
Reach Compliance Code
not_compliant
kg CO2e/kg
12.3
Average Weight (mg)
4319.45
CO2e (mg)
53129.238
YTEOL
0
控制类型
ENABLE LOW
JESD-30 代码
R-PDIP-T20
JESD-609代码
e0
负载电容(CL)
50 pF
逻辑集成电路类型
BUS DRIVER
最大I(ol)
0.012 A
湿度敏感等级
1
位数
4
功能数量
2
端口数量
2
端子数量
20
最高工作温度
70 °C
最低工作温度
输出特性
3-STATE
输出极性
INVERTED
封装主体材料
PLASTIC/EPOXY
封装代码
DIP
封装等效代码
DIP20,.3
封装形状
RECTANGULAR
封装形式
IN-LINE
峰值回流温度(摄氏度)
245
Prop。Delay @ Nom-Sup
8 ns
认证状态
Not Qualified
标称供电电压 (Vsup)
5 V
表面贴装
NO
技术
CMOS
温度等级
COMMERCIAL
端子面层
TIN LEAD
端子形式
THROUGH-HOLE
端子节距
2.54 mm
端子位置
DUAL
文档预览
IDT74FCT2240AT/CT
FAST CMOS OCTAL BUFFER/LINE DRIVER
INDUSTRIAL TEMPERATURE RANGE
FAST CMOS OCTAL
BUFFER/LINE DRIVER
IDT74FCT2240AT/CT
FEATURES:
DESCRIPTION:
A and C grades
Low input and output leakage
1µA (max.)
CMOS power levels
True TTL input and output compatibility:
– V
OH
= 3.3V (typ.)
– V
OL
= 0.3V (typ.)
Meets or exceeds JEDEC standard 18 specifications
Resistor outputs (-15mA I
OH
, 12mA I
OL
)
Reduced system switching noise
Available in SOIC and QSOP packages
The IDT octal buffer/line driver is built using an advanced dual metal
CMOS technology. The FCT2240T is designed to be employed as a
memory and address driver, clock driver, and bus-oriented transmitter/
receiver which provides improved board density.
The FCT2240T has balanced output drive with current limiting resistors.
This offers low ground bounce, minimal undershoot, and controlled output
fall times, reducing the need for external series terminating resistors. The
FCT2240T is a plug-in replacement for the FCT240T.
FUNCTIONAL BLOCK DIAGRAM
OE
A
OE
B
DA
0
OB
0
DA
1
OB
1
DA
2
OB
2
DA
3
OB
3
OA
0
DB
0
OA
1
DB
1
OA
2
DB
2
OA
3
DB
3
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
JUNE 2002
DSC-5585/2
© 2002 Integrated Device Technology, Inc.
IDT74FCT2240AT/CT
FAST CMOS OCTAL BUFFER/LINE DRIVER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
(2)
V
TERM
(3)
T
STG
I
OUT
Description
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Max
–0.5 to +7
–0.5 to V
CC
+0.5
–65 to +150
–60 to +120
Unit
V
V
°C
mA
OE
A
DA
0
OB
0
DA
1
OB
1
DA
2
OB
2
DA
3
OB
3
GND
1
2
3
4
5
6
7
8
9
10
SOIC/ QSOP
TOP VIEW
20
19
18
17
16
15
14
13
12
11
V
CC
OE
B
OA
0
DB
0
OA
1
DB
1
OA
2
DB
2
OA
3
DB
3
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
Vcc by +0.5V unless otherwise noted.
2. Inputs and Vcc terminals only.
3. Output and I/O terminals only.
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
6
8
Max.
10
12
Unit
pF
pF
NOTE:
1. This parameter is measured at characterization but not tested.
PIN DESCRIPTION
Pin Names
OE
A
,
OE
B
Dxx
Oxx
Inputs
Outputs
Description
3-State Output Enable Inputs (Active LOW)
FUNCTION TABLE
(1)
OE
A
L
L
H
Inputs
OE
B
L
L
H
D
L
H
X
Outputs
H
L
Z
NOTE:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
Z = High Impedance
2
IDT74FCT2240AT/CT
FAST CMOS OCTAL BUFFER/LINE DRIVER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= –40°C to +85°C, V
CC
= 5.0V ±5%
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
I
I
V
IK
V
H
I
CC
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
Input LOW Current
High Impedance Output Current
(3-State Output Pins)
Input HIGH Current
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Max.
V
IN
= GND or V
CC
V
CC
= Max., V
I
= V
CC
(Max.)
V
CC
= Min., I
IN
= –18mA
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
CC
= Max.
V
CC
= Max.
V
I
= 2.7V
V
I
= 0.5V
V
I
= 2.7V
V
I
= 0.5V
Min.
2
Typ.
(2)
–0.7
200
0.01
Max.
0.8
±1
±1
±1
±1
±1
–1.2
1
µA
V
mV
µA
Unit
V
V
µA
µA
µA
OUTPUT DRIVE CHARACTERISTICS
Symbol
I
ODL
I
ODH
V
OH
V
OL
Parameter
Output LOW Current
Output HIGH Current
Output HIGH Voltage
Output LOW Voltage
Test Conditions
(1)
V
CC
= 5V, V
IN
= V
IH
or V
IL
, V
OUT
= 1.5V
(3)
V
CC
= 5V, V
IN
= V
IH
or V
IL
, V
OUT
= 1.5V
(3)
V
CC
= Min
I
OH
= –15mA
V
IN
= V
IH
or V
IL
V
CC
= Min
I
OL
= 12mA
V
IN
= V
IH
or V
IL
Min.
16
-16
2.4
Typ.
(2)
48
-48
3.3
0.3
Max.
0.5
Unit
mA
mA
V
V
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
3
IDT74FCT2240AT/CT
FAST CMOS OCTAL BUFFER/LINE DRIVER
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol
∆I
CC
I
CCD
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply
Current
(4)
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max.
Outputs Open
OE
A
or
OE
B
= GND
One Input Toggling
50% Duty Cycle
I
C
Total Power Supply Current
(6)
V
CC
= Max.
Outputs Open
fi = 10MHz
50% Duty Cycle
OE
A
or
OE
B
= GND
One Bit Toggling
V
CC
= Max.
Outputs Open
fi = 2.5MHz
50% Duty Cycle
OE
A
or
OE
B
= GND
Four Bits Toggling
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
0.6
2.2
mA
V
IN
= V
CC
V
IN
= GND
Test Conditions
(1)
Min.
Typ.
(2)
0.5
0.06
Max.
2
0.12
Unit
mA
mA/
MHz
0.9
3.2
1.2
3.4
(5)
3.2
11.4
(5)
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of
∆I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP
/2+ f
i
N
i
)
I
CC
= Quiescent Current
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Output Frequency
N
i
= Number of Outputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT2240AT
Symbol
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Parameter
Propagation Delay
Dx to
Ox
Output Enable Time
Output Disable Time
Condition
(1)
C
L
= 50pF
R
L
= 500Ω
Min.
(2)
1.5
1.5
1.5
Max.
4.8
6.2
5.6
1.5
1.5
1.5
FCT2240CT
Min.
(2)
Max.
4.3
5.8
5.2
Unit
ns
ns
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
4
IDT74FCT2240AT/CT
FAST CMOS OCTAL BUFFER/LINE DRIVER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
V
CC
500Ω
V
IN
Pulse
Generator
R
T
D.U.T
.
V
OUT
7.0V
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
All Other Tests
Switch
Closed
Open
50pF
C
L
500Ω
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
Octal link
Test Circuits for All Outputs
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
t
SU
t
H
t
REM
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
Octal link
LOW-HIGH-LOW
PULSE
t
W
HIGH-LOW-HIGH
PULSE
Octal link
1.5V
1.5V
t
SU
t
H
Pulse Width
Set-Up, Hold, and Release Times
ENABLE
SAME PHASE
INPUT TRANSITION
t
PLH
OUTPUT
t
PLH
OPPOSITE PHASE
INPUT TRANSITION
t
PHL
t
PHL
3V
1.5V
0V
V
OH
1.5V
V
OL
3V
1.5V
0V
Octal link
DISABLE
3V
1.5V
CONTROL
INPUT
t
PZL
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
t
PZH
SWITCH
OPEN
3.5V
1.5V
t
PHZ
0.3V
1.5V
0V
t
PLZ
0V
3.5V
0.3V
V
OL
V
OH
0V
Octal link
Propagation Delay
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate
1.0MHz; t
F
2.5ns; t
R
2.5ns.
5
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