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74FCT2652ATSO8

SOIC-24, Reel

器件类别:逻辑    逻辑   

厂商名称:IDT (Integrated Device Technology)

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器件参数
参数名称
属性值
Brand Name
Integrated Device Technology
是否无铅
含铅
是否Rohs认证
不符合
Objectid
109045480
零件包装代码
SOIC
包装说明
SOP, SOP24,.4
针数
24
制造商包装代码
PS24
Reach Compliance Code
not_compliant
YTEOL
0
控制类型
INDEPENDENT CONTROL
计数方向
BIDIRECTIONAL
JESD-30 代码
R-PDSO-G24
JESD-609代码
e0
逻辑集成电路类型
REGISTERED BUS TRANSCEIVER
最大I(ol)
0.012 A
湿度敏感等级
1
位数
8
功能数量
1
端口数量
2
端子数量
24
最高工作温度
85 °C
最低工作温度
-40 °C
输出特性
3-STATE
输出极性
TRUE
封装主体材料
PLASTIC/EPOXY
封装代码
SOP
封装等效代码
SOP24,.4
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE
包装方法
TR
峰值回流温度(摄氏度)
225
Prop。Delay @ Nom-Sup
6.3 ns
认证状态
Not Qualified
标称供电电压 (Vsup)
5 V
表面贴装
YES
技术
CMOS
温度等级
INDUSTRIAL
端子面层
TIN LEAD
端子形式
GULL WING
端子节距
1.27 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
30
触发器类型
POSITIVE EDGE
文档预览
IDT74FCT2652AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE)
INDUSTRIAL TEMPERATURE RANGE
FAST CMOS OCTAL
TRANSCEIVER/
REGISTERS (3-STATE)
FEATURES:
IDT74FCT2652AT/CT
A and C grades
Low input and output leakage
1µA (max.)
CMOS power levels
True TTL input and output compatibility:
– V
OH
= 3.3V (typ.)
– V
OL
= 0.3V (typ.)
Resistor outputs (-15mA I
OH
, 12mA I
OL
)
Meets or exceeds JEDEC standard 18 specifications
Reduced system switching noise
Power off disable outputs permit "live insertion"
Available in SOIC and QSOP packages
DESCRIPTION:
The FCT2652T consists of a bus transceiver with 3-state D-type flip-flops
and control circuitry arranged for multiplexed transmission of data directly
from the data bus or from the internal storage registers. The FCT2652T
utilizes GAB and
GBA
signals to control the transceiver functions.
SAB and SBA control pins are provided to select either real- time or stored
data transfer. The circuitry used for select control will eliminate the typical
decoding glitch that occurs in a multiplexer during the transition between
stored and real-time data. A low input level selects real-time data and a high
selects stored data.
Data on the A or B data bus, or both, can be stored in the internal D flip-
flops by low-to-high transitions at the appropriate clock pins (CPAB or
CPBA), regardless of the select or enable control pins.
The FCT2652T have balanced drive outputs with current limiting
resistors. This offers low ground bounce, minimal undershoot and con-
trolled output fall times-reducing the need for external series terminating
resistors. FCT2652T parts are plug-in replacements for FCT652T parts.
FUNCTIONAL BLOCK DIAGRAM
GBA
GAB
CPBA
SBA
CPAB
SAB
B REG
ONE OF EIGHT CHANNELS
1D
C1
A1
A REG
1D
C1
B1
TO SEVEN OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
AUGUST 2000
DSC-5509/1
© 2000 Integrated Device Technology, Inc.
IDT74FCT2652AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE)
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
24
23
22
21
20
19
18
17
16
15
14
13
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
(2)
Description
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Max
–0.5 to +7
–0.5 to V
CC
+0.5
–65 to +150
–60 to +120
Unit
V
V
°C
mA
V
TERM
(3)
T
STG
I
OUT
CPAB
SAB
GAB
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
GND
1
2
3
4
5
6
7
8
9
10
11
12
V
CC
CPBA
SBA
GBA
B
1
B
2
B
3
B
4
B
5
B
6
B
7
B
8
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
Vcc by +0.5V unless otherwise noted.
2. Inputs and Vcc terminals only.
3. Output and I/O terminals only.
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
6
8
Max.
10
12
Unit
pF
pF
NOTE:
1. This parameter is measured at characterization but not tested.
SOIC/ QSOP
TOP VIEW
PIN DESCRIPTION
Pin Names
A
1
- A
8
B
1
- B
8
CPAB, CPBA
SAB, SBA
GAB,
GBA
Description
Data Register A Inputs
Data Register B Output
Data Register B Inputs
Data Register A Output
Clock Pulse Inputs
Output Data Source Select Inputs
Output Enable Inputs
2
IDT74FCT2652AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE)
INDUSTRIAL TEMPERATURE RANGE
FUNCTION TABLE
(1)
Inputs
GAB
H
H
X
H
L
L
L
L
L
L
H
GBA
X
X
H
H
X
L
L
L
H
H
L
CPAB
H or L
H or L
X
X
X
H or L
H or L
CPBA
H or L
H or L
X
H or L
X
X
H or L
SAB
X
X
X
X
X
X
X
X
L
H
H
SBA
X
X
X
X
X
X
L
H
X
X
H
Output
Output
Input
Output
Input
Input
Unspecified
Output
Output
(2)
Data I/O
A
1
- A
8
Input
B
1
- B
8
Input
Unspecified
Output
Input
Input
Input
(2)
Operation
Isolation
Store A and B Data
Store A, Hold B
Store A in Both Registers
Hold A, Store B
Store B in Both Registers
Real-Time B Data to A Bus
Stored B Data to A Bus
Real-Time A Data to B Bus
Stored A Data to B Bus
Stored A Data to B Bus
Stored B Data to A Bus
NOTES:
1. H = HIGH
L = LOW
X = Don't Care
= LOW-to-HIGH transition.
Select control = L: clocks can occur simultaneously.
Select control = H: clocks must be staggered in order to load both registers.
2. The data output functions may be enabled or disabled by various signals at the GAB or
GBA
inputs. Data input functions are always enabled, i.e. data at the bus pins will be stored
on every LOW-to-HIGH transition on the clock inputs.
3
IDT74FCT2652AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE)
INDUSTRIAL TEMPERATURE RANGE
BU S
A
BUS
B
BUS
A
BU S
B
GAB
L
GBA
L
CPAB
X
CPBA
X
SAB
X
SBA
L
GAB
H
GBA
H
C PAB
X
CPBA
X
SAB
L
SBA
X
Real-Time Transfer Bus B to A
Real-Time Transfer Bus A to B
BUS
A
BUS
B
BUS
A
BUS
B
GAB
X
L
L
GBA
H
X
H
CPAB
CPBA
X
SAB
X
X
X
SBA
X
X
X
GAB
H
GBA
L
CPAB
H or
CPBA
H or
SAB
H
SBA
H
X
Storage From A and/or B
Transfer Stored Data to A and/or B
4
IDT74FCT2652AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE)
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= –40°C to +85°C, V
CC
= 5.0V ±5%
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
I
I
V
IK
V
H
I
CC
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
(4)
Input LOW Current
(4)
High Impedance Output Current
(3-State output pins)
(4)
Input HIGH Current
(4)
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Max., V
I
= V
CC
(Max.)
V
CC
= Min, I
IN
= -18mA
V
CC
= Max., V
IN
= GND or V
CC
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
CC
= Max.
V
CC
= Max
V
I
= 2.7V
V
I
= 0.5V
V
O
= 2.7V
V
O
= 0.5V
Min.
2
Typ.
(2)
–0.7
200
0.01
Max.
0.8
±1
±1
±1
±1
±1
–1.2
1
µA
V
mV
µA
Unit
V
V
µA
µA
µA
OUTPUT DRIVE CHARACTERISTICS
Symbol
I
ODL
I
ODH
V
OH
V
OL
Parameter
Output LOW Current
Output HIGH Current
Output HIGH Voltage
Output LOW Voltage
Test Conditions
(1)
V
CC
= 5V, V
IN
= V
IH
or V
IL
, V
OUT
= 1.5V
(3)
V
CC
= 5V, V
IN
= V
IH
or V
IL
, V
OUT
= 1.5V
(3)
V
CC
= Min
I
OH
= –15mA
V
IN
= V
IH
or V
IL
V
CC
= Min
I
OL
= 12mA
V
IN
= V
IH
or V
IL
Min.
16
–16
2.4
Typ.
(2)
48
–48
3.3
0.3
Max.
0.5
Unit
mA
mA
V
V
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. The test limit for this parameter is ±5µA at T
A
= –55°C.
5
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