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74HC166-Q100; 74HCT166-Q100

8-bit parallel-in/serial out shift register

Rev. 1 — 25 September 2013

Product data sheet

1. General description

The 74HC166-Q100; 74HCT166-Q100 is an 8-bit serial or parallel-in/serial-out shift

and a serial output (Q7). When the parallel enable input (PE) is LOW, the data from D0 to

D7 is loaded into the shift register on the next LOW-to-HIGH transition of the clock input

(CP). When PE is HIGH, data enters the register serially at DS with each LOW-to-HIGH

transition of CP. When the clock enable input (CE) is LOW data is shifted on the

LOW-to-HIGH transitions of CP. A HIGH on CE disables the CP input. Inputs include

clamp diodes which enable the use of current limiting resistors to interface inputs to

voltages in excess of V

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits



Automotive product qualification in accordance with AEC-Q100 (Grade 1)



Specified from

40 C

to +85

C

and from

40 C

to +125

C



Synchronous parallel-to-serial applications



Synchronous serial input for easy expansion



Complies with JEDEC standard no. 7A



Input levels:



For 74HC166-Q100: CMOS level



For 74HCT166-Q100: TTL level



ESD protection:



MIL-STD-883, method 3015 exceeds 2000 V



HBM JESD22-A114F exceeds 2000 V



MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0

)



Multiple package options

3. Ordering information

Table 1.

Ordering information

Package

Temperature range Name

74HC166D-Q100

74HCT166D-Q100

74HC166PW-Q100

40 C

to +125

C

TSSOP16

40 C

to +125

C

SO16

Description

plastic small outline package; 16 leads; body

width 3.9 mm

Version

SOT109-1

Type number

plastic thin shrink small outline package; 16 leads; SOT403-1

body width 4.4 mm

NXP Semiconductors

74HC166-Q100; 74HCT166-Q100

8-bit parallel-in/serial out shift register

4. Functional diagram

aaa-008816

aaa-008817

SRG8

≥1

C1/2

2,1D

Fig 1.

Logic symbol

Fig 2.

IEC logic symbol

8-BIT PARALLEL/SERIAL-IN/

SERIAL-OUT SHIFT REGISTER

aaa-008818

Fig 3.

Functional diagram

74HC_HCT166_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 25 September 2013

2 of 19

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Product data sheet

Rev. 1 — 25 September 2013

3 of 19

74HC_HCT166_Q100

All information provided in this document is subject to legal disclaimers.

NXP Semiconductors

74HC166-Q100; 74HCT166-Q100

R RD

aaa-008819

8-bit parallel-in/serial out shift register

Fig 4.

Logic diagram

NXP Semiconductors

74HC166-Q100; 74HCT166-Q100

8-bit parallel-in/serial out shift register

5. Pinning information

5.1 Pinning

Fig 5.

Pin configuration (SO16 and TSSOP16)

5.2 Pin description

Table 2.

Symbol

D0 to D7

GND

Pin description

2, 3, 4, 5, 10, 11, 12, 14

Description

serial data input

parallel data inputs

clock enable input (active LOW)

clock input (LOW-to-HIGH edge-triggered)

ground (0 V)

asynchronous master reset (active LOW)

serial output from the last stage

parallel enable input (active LOW)

positive supply voltage

74HC_HCT166_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 25 September 2013

4 of 19

NXP Semiconductors

74HC166-Q100; 74HCT166-Q100

8-bit parallel-in/serial out shift register

6. Functional description

Table 3.

Function table

[1]

Inputs

parallel load

serial shift

hold “do nothing”

[1]

Operating modes

Qn registers



D0 to D7

Q1 to Q6

L to L

H to H

q0 to q5

q1 to q6

Output

H = HIGH voltage level;

h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;

L = LOW voltage level;

l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;

q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition;

X = don’t care;



= LOW-to-HIGH clock transition.

mode

control

inputs

shift/

load

parallel

inputs

output

serial shift

inhibit

clear

load

aaa-008820

serial shift

Fig 6.

Typical clear, shift, load, inhibit, and shift sequences

74HC_HCT166_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 25 September 2013

5 of 19

参数对比

与74HC166PW-Q100相近的元器件有：935301536118、935301537118、935301535118、74HC166D-Q100、74HCT166D-Q100。描述及对比如下：

型号	74HC166PW-Q100	935301536118	935301537118	935301535118	74HC166D-Q100	74HCT166D-Q100
描述	Parallel In Serial Out, HC/UH Series, 8-Bit, Right Direction, True Output, CMOS, PDSO16	Parallel In Serial Out, HC/UH Series, 8-Bit, Right Direction, True Output, CMOS, PDSO16	Parallel In Serial Out, HCT Series, 8-Bit, Right Direction, True Output, CMOS, PDSO16	Parallel In Serial Out, HC/UH Series, 8-Bit, Right Direction, True Output, CMOS, PDSO16	Parallel In Serial Out, HC/UH Series, 8-Bit, Right Direction, True Output, CMOS, PDSO16	Parallel In Serial Out, HCT Series, 8-Bit, Right Direction, True Output, CMOS, PDSO16
是否Rohs认证	符合	符合	符合	符合	符合	符合
厂商名称	Nexperia	Nexperia	Nexperia	Nexperia	Nexperia	Nexperia
包装说明	TSSOP,	TSSOP,	3.90 MM, PLASTIC, MS-012, SOT109-1, SOP-16	3.90 MM, PLASTIC, MS-012, SOT109-1, SOP-16	SOP-16	SOP-16
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant
计数方向	RIGHT	RIGHT	RIGHT	RIGHT	RIGHT	RIGHT
系列	HC/UH	HC/UH	HCT	HC/UH	HC/UH	HCT
JESD-30 代码	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16
JESD-609代码	e4	e4	e4	e4	e4	e4
长度	5 mm	5 mm	9.9 mm	9.9 mm	9.9 mm	9.9 mm
逻辑集成电路类型	PARALLEL IN SERIAL OUT	PARALLEL IN SERIAL OUT	PARALLEL IN SERIAL OUT	PARALLEL IN SERIAL OUT	PARALLEL IN SERIAL OUT	PARALLEL IN SERIAL OUT
湿度敏感等级	1	1	1	1	1	1
位数	8	8	8	8	8	8
功能数量	1	1	1	1	1	1
端子数量	16	16	16	16	16	16
最高工作温度	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C
最低工作温度	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
输出极性	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	TSSOP	TSSOP	SOP	SOP	SOP	SOP
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE
传播延迟（tpd）	225 ns	225 ns	60 ns	225 ns	225 ns	60 ns
筛选级别	AEC-Q100	AEC-Q100	AEC-Q100	AEC-Q100	AEC-Q100	AEC-Q100
座面最大高度	1.1 mm	1.1 mm	1.75 mm	1.75 mm	1.75 mm	1.75 mm
最大供电电压 (Vsup)	6 V	6 V	5.5 V	6 V	6 V	5.5 V
最小供电电压 (Vsup)	2 V	2 V	4.5 V	2 V	2 V	4.5 V
标称供电电压 (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V
表面贴装	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE
端子面层	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag)	Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag)	Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag)	Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag)
端子形式	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
端子节距	0.65 mm	0.65 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm
端子位置	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
触发器类型	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE
宽度	4.4 mm	4.4 mm	3.9 mm	3.9 mm	3.9 mm	3.9 mm
最小 fmax	24 MHz	24 MHz	17 MHz	24 MHz	24 MHz	17 MHz
Base Number Matches	1	1	1	1	1	1