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74HC30D-Q100J

74HC(T)30-Q100 - 8-input NAND gate SOIC 14-Pin

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厂商名称:NXP(恩智浦)

厂商官网:https://www.nxp.com

器件标准:

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器件参数
参数名称
属性值
Brand Name
NXP Semiconductor
是否Rohs认证
符合
厂商名称
NXP(恩智浦)
零件包装代码
SOIC
包装说明
3.90 MM, PLASTIC, MS-012, SOT108-1, SOP-14
针数
14
制造商包装代码
SOT108-1
Reach Compliance Code
compliant
Base Number Matches
1
文档预览
74HC30-Q100; 74HCT30-Q100
8-input NAND gate
Rev. 1 — 30 January 2013
Product data sheet
1. General description
The 74HC30-Q100; 74HCT30-Q100 is an 8-input NAND gate. Inputs include clamp
diodes. This enables the use of current limiting resistors to interface inputs to voltages in
excess of V
CC
.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Complies with JEDEC standard JESD7A
Input levels:
For 74HC30-Q100: CMOS level
For 74HCT30-Q100: TTL level
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
Multiple package options
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74HC30D-Q100
74HCT30D-Q100
74HC30PW-Q100
74HCT30PW-Q100
40 C
to +125
C
TSSOP14
40 C
to +125
C
SO14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT402-1
Type number
NXP Semiconductors
74HC30-Q100; 74HCT30-Q100
8-input NAND gate
4. Functional diagram
1
2
3
4
5
6
11
12
A
B
C
D
E
F
G
H
mna488
1
2
3
Y
8
4
5
6
11
12
&
8
mna489
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
A
B
C
D
Y
E
mna490
F
G
H
Fig 3.
Logic diagram
74HC_HCT30_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 30 January 2013
2 of 14
NXP Semiconductors
74HC30-Q100; 74HCT30-Q100
8-input NAND gate
5. Pinning information
5.1 Pinning
+&4
+&74
$
%
&
'
(
)
*1'







DDD
 9
&&
 QF
 +
 *
 QF


QF
<
Fig 4.
Pin configuration SO14 and TSSOP14
5.2 Pin description
Table 2.
Symbol
A
B
C
D
E
F
GND
Y
n.c.
n.c.
G
H
n.c.
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
data input
data input
data input
data input
data input
data input
ground (0 V)
data output
not connected
not connected
data input
data input
not connected
supply voltage
74HC_HCT30_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 30 January 2013
3 of 14
NXP Semiconductors
74HC30-Q100; 74HCT30-Q100
8-input NAND gate
6. Functional description
Table 3.
Input
A
L
X
X
X
X
X
X
X
H
[1]
Function table
[1]
Output
B
X
L
X
X
X
X
X
X
H
C
X
X
L
X
X
X
X
X
H
D
X
X
X
L
X
X
X
X
H
E
X
X
X
X
L
X
X
X
H
F
X
X
X
X
X
L
X
X
H
G
X
X
X
X
X
X
L
X
H
H
X
X
X
X
X
X
X
L
H
Y
H
H
H
H
H
H
H
H
L
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
SO14 and TSSOP14
packages
[1]
[2]
[2]
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
0.5
V < V
O
< V
CC
+ 0.5 V
[1]
[1]
Min
0.5
-
-
-
-
50
65
-
Max
+7
20
20
25
50
-
+150
500
Unit
V
mA
mA
mA
mA
mA
C
mW
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SO14 package: P
tot
derates linearly with 8 mW/K above 70
C.
For TSSOP14 packages: P
tot
derates linearly with 5.5 mW/K above 60
C.
74HC_HCT30_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 30 January 2013
4 of 14
NXP Semiconductors
74HC30-Q100; 74HCT30-Q100
8-input NAND gate
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
V
CC
V
I
V
O
T
amb
t/V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Conditions
74HC30-Q100
Min
2.0
0
0
40
-
-
-
Typ
5.0
-
-
-
-
1.67
-
Max
6.0
V
CC
V
CC
+125
625
139
83
74HCT30-Q100
Min
4.5
0
0
40
-
-
-
Typ
5.0
-
-
-
-
1.67
-
Max
5.5
V
CC
V
CC
+125
-
139
-
V
V
V
C
ns/V
ns/V
ns/V
Unit
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
74HC30-Q100
V
IH
HIGH-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
OH
HIGH-level
output voltage
V
I
= V
IH
or V
IL
I
O
=
20 A;
V
CC
= 2.0 V
I
O
=
20 A;
V
CC
= 4.5 V
I
O
=
20 A;
V
CC
= 6.0 V
I
O
=
4.0
mA; V
CC
= 4.5 V
I
O
=
5.2
mA; V
CC
= 6.0 V
V
OL
LOW-level
output voltage
V
I
= V
IH
or V
IL
I
O
= 20
A;
V
CC
= 2.0 V
I
O
= 20
A;
V
CC
= 4.5 V
I
O
= 20
A;
V
CC
= 6.0 V
I
O
= 4.0 mA; V
CC
= 4.5 V
I
O
= 5.2 mA; V
CC
= 6.0 V
I
I
I
CC
input leakage
current
supply current
V
I
= V
CC
or GND;
V
CC
= 6.0 V
V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 6.0 V
-
-
-
-
-
-
-
0
0
0
0.15
0.16
-
-
0.1
0.1
0.1
0.26
0.26
0.1
2.0
-
-
-
-
-
-
-
0.1
0.1
0.1
0.33
0.33
1
20
-
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
1
40
V
V
V
V
V
A
A
1.9
4.4
5.9
3.98
5.48
2.0
4.5
6.0
4.32
5.81
-
-
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
1.5
3.15
4.2
-
-
-
1.2
2.4
3.2
0.8
2.1
2.8
-
-
-
0.5
1.35
1.8
1.5
3.15
4.2
-
-
-
-
-
-
0.5
1.35
1.8
1.5
3.15
4.2
-
-
-
-
-
-
0.5
1.35
1.8
V
V
V
V
V
V
Conditions
Min
25
C
Typ
Max
40 C
to +85
C 40 C
to +125
C
Unit
Min
Max
Min
Max
74HC_HCT30_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 30 January 2013
5 of 14
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